Minimal acyclic forbidden minors for the family of graphs with bounded path-width A Takahashi, S Ueno, Y Kajitani Discrete Mathematics 127 (1-3), 293-304, 1994 | 97 | 1994 |
Mixed searching and proper-path-width A Takahashi, S Ueno, Y Kajitani Theoretical Computer Science 137 (2), 253-268, 1995 | 92 | 1995 |
Routability of FPGAs with Extremal Switch-Block Structures Y Takashima, A Takahashi, Y Kajitani IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 1998 | 91 | 1998 |
Performance and reliability driven clock scheduling of sequential logic circuits A Takahashi, Y Kajitani Proceedings of ASP-DAC'97: Asia and South Pacific Design Automation …, 1997 | 64 | 1997 |
Self-aligned double and quadruple patterning-aware grid routing with hotspots control C Kodama, H Ichikawa, K Nakayama, T Kotani, S Nojima, S Mimotogi, ... 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 267-272, 2013 | 44 | 2013 |
A global routing method for 2-layer ball grid array packages Y Kubo, A Takahashi Proceedings of the 2005 international symposium on Physical design, 36-43, 2005 | 38 | 2005 |
Optimal integer delay budgeting on directed acyclic graphs E Bozorgzadeh, S Ghiasi, A Takahashi, M Sarrafzadeh Proceedings of the 40th annual Design Automation Conference, 920-925, 2003 | 38 | 2003 |
Monotonic parallel and orthogonal routing for single-layer ball grid array packages Y Tomioka, A Takahashi Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 33 | 2006 |
Global routing by iterative improvements for two-layer ball grid array packages Y Kubo, A Takahashi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 32 | 2006 |
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits A Takahashi, K Inoue, Y Kajitani Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM …, 1997 | 31 | 1997 |
A Fast Process Variation and Pattern Fidelity Aware Mask Optimization Algorithm A Awad, A Takahashi, S Tanaka, C Kodama Proc. IEEE/ACM 2014 International Conference on Computer-Aided Design (ICCAD …, 2014 | 28 | 2014 |
Passenger estimation system using Wi-Fi probe request W Pattanusorn, I Nilkhamhang, S Kittipiyakul, K Ekkachai, A Takahashi 7th International Conference on Information Communication Technology for …, 2016 | 26 | 2016 |
CAFE router: A fast connectivity aware multiple nets routing algorithm for routing grid with obstacles Y Kohira, A Takahashi IEICE transactions on fundamentals of electronics, communications and …, 2010 | 26 | 2010 |
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. Y Kohira, A Takahashi Proc. Asia and South Pacific Design Automation Conference 2010 (ASP-DAC 2010 …, 2010 | 26 | 2010 |
Practical fast clock-schedule design algorithms A Takahashi IEICE Transactions on Fundamentals of Electronics, Communications and …, 2006 | 26 | 2006 |
Clock period minimization method of semi-synchronous circuits by delay insertion Y Kohira, A Takahashi IEICE transactions on fundamentals of electronics, communications and …, 2005 | 26 | 2005 |
Indoor room identify and mapping with virtual based SLAM using furnitures and household objects relationship based on CNNs P Maolanon, K Sukvichai, N Chayopitak, A Takahashi 2019 10th International Conference of Information and Communication …, 2019 | 22 | 2019 |
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound Y Kohira, S Suehiro, A Takahashi IEICE Transactions on Fundamentals of Electronics, Communications and …, 2009 | 22 | 2009 |
A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound Y Kohira, S Suehiro, A Takahashi Proc. Asia and South Pacific Design Automation Conference 2009 (ASP-DAC 2009 …, 2009 | 22 | 2009 |
Clock period minimization of semi-synchronous circuits by gate-level delay insertion T Yoda, A Takahashi IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 1999 | 20 | 1999 |