Vinay C Patil
TitleCited byYear
Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques
A Vijayakumar, VC Patil, DE Holcomb, C Paar, S Kundu
IEEE Transactions on Information Forensics and Security 12 (1), 64-77, 2016
462016
Machine learning resistant strong PUF: Possible or a pipe dream?
A Vijayakumar, VC Patil, CB Prado, S Kundu
2016 IEEE international symposium on hardware oriented security and trustá…, 2016
432016
On design of temperature invariant physically unclonable functions based on ring oscillators
R Kumar, VC Patil, S Kundu
2012 IEEE Computer Society Annual Symposium on VLSI, 165-170, 2012
292012
Design of unique and reliable physically unclonable functions based on current starved inverter chain
R Kumar, VC Patil, S Kundu
2011 IEEE Computer Society Annual Symposium on VLSI, 224-229, 2011
182011
Realizing strong PUF from weak PUF via neural computing
L Santiago, VC Patil, CB Prado, TAO Alves, LAJ Marzulo, FMG Franša, ...
2017 IEEE international symposium on defect and fault tolerance in VLSI andá…, 2017
102017
On improving reliability of SRAM-based physically unclonable functions
A Vijayakumar, VC Patil, S Kundu
Journal of Low Power Electronics and Applications 7 (1), 2, 2017
82017
Improving reliability of weak PUFs via circuit techniques to enhance mismatch
VC Patil, A Vijayakumar, DE Holcomb, S Kundu
2017 IEEE International Symposium on Hardware Oriented Security and Trustá…, 2017
72017
Determining proximal geolocation of IoT edge devices via covert channel
MN Islam, VC Patil, S Kundu
2017 18th International Symposium on Quality Electronic Design (ISQED), 196-202, 2017
72017
An efficient method for clock skew scheduling to reduce peak current
A Vijayakumar, VC Patil, S Kundu
2016 29th International Conference on VLSI Design and 2016 15thá…, 2016
72016
On testing physically unclonable functions for uniqueness
A Vijayakumar, VC Patil, S Kundu
2016 17th International symposium on quality electronic design (ISQED), 368-373, 2016
62016
On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging
MN Islam, VC Patil, S Kundu
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (3), 960-969, 2018
52018
On pattern generation for maximizing IR drop
A Vijayakumar, VC Patil, G Paladugu, S Kundu
Fifteenth International Symposium on Quality Electronic Design, 731-737, 2014
52014
A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF
MN Islam, VC Patil, S Kundu
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
42017
Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment
P Ramesh, VC Patil, S Kundu
2017 IEEE North Atlantic test workshop (NATW), 1-4, 2017
42017
Manufacturer turned attacker: Dangers of stealthy trojans via threshold voltage manipulation
VC Patil, A Vijayakumar, S Kundu
2017 IEEE North Atlantic Test Workshop (NATW), 1-6, 2017
32017
On meta-obfuscation of physical layouts to conceal design characteristics
VC Patil, A Vijayakumar, S Kundu
2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI andá…, 2016
32016
Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs
HL Franša, CB Prado, VC Patil, S Kundu
2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 25-30, 2018
22018
Efficient Testing of Physically Unclonable Functions for Uniqueness
LS de Ara˙jo, VC Patil, LAJ Marzulo, FMG Franša, S Kundu
2019 IEEE 28th Asian Test Symposium (ATS), 117-1175, 2019
2019
Design of Robust, High-Entropy Strong PUFs via Weightless Neural Network
LS de Ara˙jo, VC Patil, CB Prado, TAO Alves, LAJ Marzulo, FMG Franša, ...
Journal of Hardware and Systems Security 3 (3), 235-249, 2019
2019
Preventing integrated circuit piracy via custom encoding of hardware instruction set
VC Patil, A Vijayakumar, S Kundu
2016 17th International Symposium on Quality Electronic Design (ISQED), 234-241, 2016
2016
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Articles 1–20