Follow
Fabian Schuiki
Fabian Schuiki
SiFive, ETH Zurich
Verified email at sifive.com - Homepage
Title
Cited by
Cited by
Year
A scalable near-memory architecture for training deep neural networks on large in-memory datasets
F Schuiki, M Schaffner, FK Gürkaynak, L Benini
IEEE Transactions on Computers 68 (4), 484-497, 2018
732018
Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with multiprecision floating-point support in 22-nm FD-SOI
M Cavalcante, F Schuiki, F Zaruba, M Schaffner, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (2), 530-543, 2019
452019
LLHD: A multi-level intermediate representation for hardware description languages
F Schuiki, A Kurth, T Grosser, L Benini
Proceedings of the 41st ACM SIGPLAN Conference on Programming Language …, 2020
312020
FPnew: An open-source multiformat floating-point unit architecture for energy-proportional transprecision computing
S Mach, F Schuiki, F Zaruba, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 774-787, 2020
272020
Manticore: A 4096-core RISC-V chiplet architecture for ultraefficient floating-point computing
F Zaruba, F Schuiki, L Benini
IEEE Micro 41 (2), 36-42, 2020
252020
Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads
F Zaruba, F Schuiki, T Hoefler, L Benini
IEEE Transactions on Computers 70 (11), 1845-1860, 2020
242020
An open-source platform for high-performance non-coherent on-chip communication
A Kurth, W Rönninger, T Benz, M Cavalcante, F Schuiki, F Zaruba, ...
IEEE Transactions on Computers 71 (8), 1794-1809, 2021
182021
Stream semantic registers: A lightweight RISC-V ISA extension achieving full compute utilization in single-issue cores
F Schuiki, F Zaruba, T Hoefler, L Benini
IEEE Transactions on Computers 70 (2), 212-227, 2020
172020
A 0.80 pJ/flop, 1.24 Tflop/sW 8-to-64 bit transprecision floating-point unit for a 64 bit RISC-V processor in 22nm FD-SOI
S Mach, F Schuiki, F Zaruba, L Benini
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019
122019
NTX: An energy-efficient streaming accelerator for floating-point generalized reduction workloads in 22 nm FD-SOI
F Schuiki, M Schaffner, L Benini
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 662-667, 2019
102019
The floating point trinity: A multi-modal approach to extreme energy-efficiency and performance
F Zaruba, F Schuiki, S Mach, L Benini
2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019
92019
Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems
M Cavalcante, A Kurth, F Schuiki, L Benini
Proceedings of the 17th ACM International Conference on Computing Frontiers …, 2020
82020
Indirection stream semantic register architecture for efficient sparse-dense linear algebra
P Scheffler, F Zaruba, F Schuiki, T Hoefler, L Benini
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
62021
Snitch: A 10 kGE pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads
F Zaruba, F Schuiki, T Hoefler, L Benini
62020
MLIR as hardware compiler infrastructure
S Eldridge, P Barua, A Chapyzhenka, A Izraelevitz, J Koenig, C Lattner, ...
Workshop on Open-Source EDA Technology (WOSET), 2021
42021
Live demonstration: Exploiting body-biasing for static corner trimming and maximum energy efficiency operation in 22nm FDX technology
A Di Mauro, F Zaruba, F Schuiki, S Mach, L Benini
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2020
32020
A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
F Zaruba, F Schuiki, L Benini
2020 IEEE Hot Chips 32 Symposium (HCS), 1-24, 2020
32020
Ntx: An energyefficient streaming accelerator for floating-point generalized reduction workloads in 22 nm fd-soi. In 2019 Design, Automation & Test in Europe Conference …
F Schuiki, M Schaffner, L Benini
IEEE, 2019
22019
Streaming architectures for extreme energy efficiency in high-performance computing
F Schuiki
ETH Zurich, 2021
12021
XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs
D Diamantopoulos, F Scheidegger, S Mach, F Schuiki, G Haugou, ...
2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2020
12020
The system can't perform the operation now. Try again later.
Articles 1–20