| DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters AMC Martinez, L Gerlach, G Payá-Vayá, H Hermansky, J Ooster, ... Speech Communication 106, 44-56, 2019 | 20 | 2019 |
| Customizing a vliw-simd application-specific instruction-set processor for hearing aid devices J Hartig, L Gerlach, G Payá-Vayá, H Blume 2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014 | 16 | 2014 |
| An area efficient real-and complex-valued multiply-accumulate SIMD unit for digital signal processors L Gerlach, G Payá-Vayá, H Blume 2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015 | 14 | 2015 |
| A survey on application specific processor architectures for digital hearing aids L Gerlach, G Paya-Vaya, H Blume Journal of Signal Processing Systems, 1-16, 2022 | 12 | 2022 |
| Flint: Layout-oriented fpga-based methodology for fault tolerant asic design R Nowosielski, L Gerlach, S Bieband, G Payá-Vayá, H Blume 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 297-300, 2015 | 12 | 2015 |
| Evolutionary algorithms for instruction scheduling, operation merging, and register allocation in VLIW compilers F Giesemann, L Gerlach, G Paya-Vaya Journal of Signal Processing Systems 92 (7), 655-678, 2020 | 10 | 2020 |
| Using a genetic algorithm approach to reduce register file pressure during instruction scheduling F Giesemann, G Payá-Vayá, L Gerlach, H Blume, F Pflug, G von Voigt 2017 International Conference on Embedded Computer Systems: Architectures …, 2017 | 9 | 2017 |
| Efficient emulation of floating-point arithmetic on fixed-point SIMD processors L Gerlach, G Payá-Vayá, H Blume 2016 IEEE International Workshop on Signal Processing Systems (SiPS), 254-259, 2016 | 9 | 2016 |
| Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP L Gerlach, G Payá-Vayá, S Liu, M Weißbrich, H Blume, D Marquardt, ... 2017 International Conference on Embedded Computer Systems: Architectures …, 2017 | 8 | 2017 |
| Kavuaka: A low power application specific hearing aid processor L Gerlach, G Paya-Vaya, H Blume 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 7 | 2019 |
| Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor C Seifert, J Thiemann, L Gerlach, T Volkmar, G Payá-Vayá, H Blume, ... 2017 IEEE International Conference on Multimedia and Expo (ICME), 145-150, 2017 | 6 | 2017 |
| SmartHeaP-A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI J Karrenbauer, S Klein, S Schönewald, L Gerlach, M Blawat, J Benndorf, ... ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 5 | 2022 |
| FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework M Weißbrich, L Gerlach, H Blume, A Najafi, A García-Ortiz, G Payá-Vayá Integration 69, 120-137, 2019 | 5 | 2019 |
| Design space exploration framework for tensilica-based digital audio processors in hearing aids J Karrenbauer, L Gerlach, G Payá-Vayá, H Blume 2020 9th International Conference on Modern Circuits and Systems …, 2020 | 4 | 2020 |
| A Low Latency Multichannel Audio Interface for Low Power SIMD Digital Signal Processors L Gerlach, G Payá-Vayá, H Blume ICT. OPEN 2016, 2016 | 3 | 2016 |
| Issue-Slot Based Predication Encoding Technique for VLIW Processors L Gerlach, F Stuckmann, H Blume, G Payá-Vayá 2020 9th International Conference on Modern Circuits and Systems …, 2020 | 2 | 2020 |
| A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor Architectures L Gerlach, S Nolting, H Blume, GP Vayá, H Stolberg, C Reuter Technology Transfer in Computing Systems (TETRACOM Technology Transfer …, 2016 | 2 | 2016 |
| Methodology for Observation and Evaluation of Fault Tolerance Implementations inside High Temperature ASICs R Nowosielski, L Gerlach, G Payá-Vayá, S Hesselbarth, H Blume ICT. OPEN 11, 2013, 2013 | 1 | 2013 |
| KAVUAKA: a low-power application-specific processor architecture for digital hearing aids L Gerlach Hannover: Institutionelles Repositorium der Leibniz Universität Hannover, 2021 | | 2021 |
| Design Space Exploration of Hardware Architectures for Hearing Aid Devices G Paya-Vaya, J Hartig, L Gerlach, H Blume BIOMEDICAL ENGINEERING-BIOMEDIZINISCHE TECHNIK 59, S733-S733, 2014 | | 2014 |
