Raghavendra Kanakagiri
Raghavendra Kanakagiri
Indian Institute of Technology Tirupati
Verified email at - Homepage
Cited by
Cited by
Sisa: Set-centric instruction set architecture for graph mining on processing-in-memory systems
M Besta, R Kanakagiri, G Kwasniewski, R Ausavarungnirun, J BerŠnek, ...
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture†…, 2021
Communication-efficient jaccard similarity for high-performance distributed genome comparisons
M Besta, R Kanakagiri, H Mustafa, M Karasikov, G Rštsch, T Hoefler, ...
2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS†…, 2020
Motif prediction with graph neural networks
M Besta, R Grob, C Miglioli, N Bernold, G Kwasniewski, G Gjini, ...
Proceedings of the 28th ACM SIGKDD Conference on Knowledge Discovery and†…, 2022
MBZip: Multiblock data compression
R Kanakagiri, B Panda, M Mutyam
ACM Transactions on Architecture and Code Optimization (TACO) 14 (4), 1-29, 2017
The Charm++ parallel programming system
L Kalť, B Acun, S Bak, A Becker, M Bhandarkar, N Bhat, A Bhatele, ...
Aug, 2019
Scalable GW software for quasiparticle properties using OpenAtom
M Kim, S Mandal, E Mikida, K Chandrasekar, E Bohm, N Jain, Q Li, ...
Computer Physics Communications 244, 427-441, 2019
Probgraph: High-performance and high-accuracy graph mining with probabilistic set representations
M Besta, C Miglioli, PS Labini, J Tětek, P Iff, R Kanakagiri, S Ashkboos, ...
SC22: International Conference for High Performance Computing, Networking†…, 2022
Process variation aware issue queue design
K Raghavendra, M Mutyam
2008 Design, Automation and Test in Europe, 1438-1443, 2008
Pbc: Prefetched blocks compaction
K Raghavendra, B Panda, M Mutyam
IEEE Transactions on Computers 65 (8), 2534-2547, 2015
SkipCache: application aware cache management for chip multi‐processors
TS Warrier, K Raghavendra, M Mutyam
IET Computers & Digital Techniques 9 (6), 293-299, 2015
High-Performance and Programmable Attentional Graph Neural Networks with Global Tensor Formulations
M Besta, P Renc, R Gerstenberger, P Sylos Labini, A Ziogas, T Chen, ...
Proceedings of the International Conference for High Performance Computing†…, 2023
Parallel minimum spanning forest computation using sparse matrix kernels
T Baer, R Kanakagiri, E Solomonik
Proceedings of the 2022 SIAM Conference on Parallel Processing for†…, 2022
Router buffer caching for managing shared cache blocks in tiled multi-core processors
J Augustine, K Raghavendra, J Jose, M Mutyam
2020 IEEE 38th International Conference on Computer Design (ICCD), 239-246, 2020
SkipCache: Miss-rate aware cache management
K Raghavendra, TS Warrier, M Mutyam
2012 21st International Conference on Parallel Architectures and Compilation†…, 2012
Minimum cost loop nests for contraction of a sparse tensor with a tensor network
R Kanakagiri, E Solomonik
arXiv preprint arXiv:2307.05740, 2023
Process variation aware issue queue design
M Mutyam, K Raghavendra
Optimizing Distributed Tensor Contractions Using Node-Aware Processor Grids
A Irmler, R Kanakagiri, ST Ohlmann, E Solomonik, A GrŁneis
European Conference on Parallel Processing, 710-724, 2023
Determination of Checkpointing Intervals for Malleable Applications
K Raghavendra, SS Vadhiyar
arXiv preprint arXiv:1711.00270, 2017
SAMO: store aware memory optimizations
K Raghavendra, T Warrier, M Mutyam
Proceedings of the 11th ACM Conference on Computing Frontiers, 1-10, 2014
MBZip: A Case for Compressing Multiple Data Blocks
K Raghavendra, B Panda, M Mutyam
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