Gioele Mirabelli
Gioele Mirabelli
R&D Design Engineer
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Cited by
Cited by
Air sensitivity of MoS2, MoSe2, MoTe2, HfS2, and HfSe2
G Mirabelli, C McGeough, M Schmidt, EK McCarthy, S Monaghan, ...
Journal of Applied Physics 120 (12), 2016
Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance–voltage analysis
P Zhao, A Khosravi, A Azcatl, P Bolshakov, G Mirabelli, E Caruso, ...
2D Materials 5 (3), 031002, 2018
Quantum confinement-induced semimetal-to-semiconductor evolution in large-area ultra-thin PtSe2 films grown at 400 °C
L Ansari, S Monaghan, N McEvoy, CÓ Coileáin, CP Cullen, J Lin, R Siris, ...
npj 2D Materials and Applications 3 (1), 33, 2019
DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies
MG Bardon, P Wuytens, LÅ Ragnarsson, G Mirabelli, D Jang, G Willems, ...
2020 IEEE International Electron Devices Meeting (IEDM), 41.4. 1-41.4. 4, 2020
Back-gated Nb-doped MoS2 junctionless field-effect-transistors
G Mirabelli, M Schmidt, B Sheehan, K Cherkaoui, S Monaghan, I Povey, ...
AIP Advances 6 (2), 2016
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
P Schuddinck, FM Bufler, Y Xiang, A Farokhnejad, G Mirabelli, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
Investigating the transient response of Schottky barrier back-gated MoS2 transistors
C Marquez, N Salazar, F Gity, C Navarro, G Mirabelli, JC Galdon, R Duffy, ...
2D Materials 7 (2), 025040, 2020
Physics-based modelling of MoS2: the layered structure concept
G Mirabelli, PK Hurley, R Duffy
Semiconductor Science and Technology 34 (5), 055015, 2019
Exploring conductivity in ex-situ doped Si thin films as thickness approaches 5 nm
J MacHale, F Meaney, N Kennedy, L Eaton, G Mirabelli, M White, ...
Journal of Applied Physics 125 (22), 2019
Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
B Chehab, J Ryckaert, P Schuddinck, P Weckx, N Horiguchi, G Mirabelli, ...
Design-Process-Technology Co-optimization XV 11614, 59-63, 2021
Formation and characterization of Ni, Pt, and Ti stanogermanide contacts on Ge0. 92Sn0. 08
E Galluccio, N Petkov, G Mirabelli, J Doherty, SY Lin, FL Lu, CW Liu, ...
Thin Solid Films 690, 137568, 2019
Effects of Annealing Temperature and Ambient on Metal/PtSe2 Contact Alloy Formation
G Mirabelli, LA Walsh, F Gity, S Bhattacharjee, CP Cullen, C Ó Coileáin, ...
ACS omega 4 (17), 17487-17493, 2019
Impact of impurities, interface traps and contacts on MoS2 MOSFETs: Modelling and experiments
G Mirabelli, F Gity, S Monaghan, PK Hurley, R Duffy
2017 47th European Solid-State Device Research Conference (ESSDERC), 288-291, 2017
Structural and Electrical Investigation of MoS2 Thin Films Formed by Thermal Assisted Conversion of Mo Metal
R Duffy, P Foley, B Filippone, G Mirabelli, D O'Connell, B Sheehan, ...
ECS Journal of Solid State Science and Technology 5 (11), Q3016, 2016
From Design to System-Technology optimization for CMOS
J Ryckaert, B Chehab, D Jang, G Mirabelli, SM Salahuddin, P Schuddinck, ...
2021 International Symposium on VLSI Technology, Systems and Applications …, 2021
Cell formation in stanogermanides using pulsed laser thermal anneal on Ge0. 91Sn0. 09
E Galluccio, G Mirabelli, A Harvey, M Conroy, E Napolitani, R Duffy
Materials Science in Semiconductor Processing 121, 105399, 2021
Monolayer doping of silicon-germanium alloys: A balancing act between phosphorus incorporation and strain relaxation
N Kennedy, R Duffy, G Mirabelli, L Eaton, N Petkov, JD Holmes, C Hatem, ...
Journal of Applied Physics 126 (2), 2019
Investigating Interface States and Oxide Traps in the MoS2/Oxide/Si System
E Coleman, G Mirabelli, P Bolshakov, P Zhao, E Caruso, F Gity, ...
Solid-State Electronics, 108123, 2021
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node
G Sisto, R Preston, R Chen, G Mirabelli, A Farokhnejad, Y Zhou, I Ciofi, ...
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology
S Yang, P Schuddinck, M Garcia-Bardon, Y Xiang, A Veloso, BT Chan, ...
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023
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