Matthias Sauer
Matthias Sauer
Verified email at informatik.uni-freiburg.de - Homepage
Title
Cited by
Cited by
Year
Small-delay-fault ATPG with waveform accuracy
M Sauer, A Czutro, I Polian, B Becker
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 30-36, 2012
542012
Equivalence checking of partial designs using dependency quantified Boolean formulae
K Gitina, S Reimer, M Sauer, R Wimmer, C Scholl, B Becker
2013 IEEE 31st International Conference on Computer Design (ICCD), 396-403, 2013
312013
Efficient SAT-based search for longest sensitisable paths
M Sauer, J Jiang, A Czutro, I Polian, B Becker
2011 Asian Test Symposium, 108-113, 2011
302011
A flexible framework for the automatic generation of sbst programs
A Riefert, R Cantoro, M Sauer, MS Reorda, B Becker
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10†…, 2016
292016
Solving DQBF through quantifier elimination
K Gitina, R Wimmer, S Reimer, M Sauer, C Scholl, B Becker
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE†…, 2015
282015
Functional test of small-delay faults using SAT and Craig interpolation
M Sauer, S Kupferschmid, A Czutro, I Polian, S Reddy, B Becker
2012 IEEE International Test Conference, 1-8, 2012
232012
SAT-based analysis of sensitisable paths
M Sauer, A Czutro, T Schubert, S Hillebrecht, I Polian, B Becker
14th IEEE International Symposium on Design and Diagnostics of Electronic†…, 2011
212011
On the automatic generation of SBST test programs for in-field test
A Riefert, R Cantoro, M Sauer, MS Reorda, B Becker
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE†…, 2015
202015
An effective approach to automatic functional processor test generation for small-delay faults
A Riefert, L Ciganda, M Sauer, P Bernardi, MS Reorda, B Becker
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
202014
On the optimality of K longest path generation algorithm under memory constraints
J Jiang, M Sauer, A Czutro, B Becker, I Polian
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 418-423, 2012
182012
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
M Sauer, S Reimer, T Schubert, I Polian, B Becker
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 448-453, 2013
172013
Formal verification of secure reconfigurable scan network infrastructure
MA Kochte, R Baranowski, M Sauer, B Becker, HJ Wunderlich
2016 21th IEEE European Test Symposium (ETS), 1-6, 2016
162016
Provably Optimal Test Cube Generation using Quantified Boolean Formula Solving
M Sauer, S Reimer, I Polian, T Schubert, B Becker
Asia and South Pacific Design Automation Conference (ASP-DAC), 2013
162013
SAT-ATPG using preferences for improved detection of complex defect mechanisms
A Czutro, M Sauer, T Schubert, I Polian, B Becker
2012 IEEE 30th VLSI Test Symposium (VTS), 170-175, 2012
162012
Specification and verification of security in reconfigurable scan networks
MA Kochte, M Sauer, LR Gomez, P Raiola, B Becker, HJ Wunderlich
2017 22nd IEEE European Test Symposium (ETS), 1-6, 2017
152017
Efficient SMT-based ATPG for interconnect open defects
D Erb, K Scheibler, M Sauer, B Becker
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
152014
Early-life-failure detection using SAT-based ATPG
M Sauer, YM Kim, J Seomun, HO Kim, KT Do, JY Choi, KS Kim, S Mitra, ...
2013 IEEE International Test Conference (ITC), 1-10, 2013
152013
Variation-Aware Fault Grading
A Czutro, ME Imhof, J Jiang, A Mumtaz, M Sauer, B Becker, I Polian, ...
152012
PHAETON: A SAT-based framework for timing-aware path sensitization
M Sauer, B Becker, I Polian
IEEE Transactions on Computers 65 (6), 1869-1881, 2015
142015
Identification of high power consuming areas with gate type and logic level information
K Miyase, M Sauer, B Becker, X Wen, S Kajihara
2015 20th IEEE European Test Symposium (ETS), 1-6, 2015
142015
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