A 1.25-GS/s 7-b SAR ADC with 36.4-dB SNDR at 5 GHz using switch-bootstrapping, USPC DAC and triple-tail comparator in 28-nm CMOS AT Ramkaj, M Strackx, MSJ Steyaert, F Tavernier IEEE Journal of Solid-State Circuits 53 (7), 1889-1901, 2018 | 112 | 2018 |
A 5-GS/s 158.6-mW 9.4-ENOB passive-sampling time-interleaved three-stage pipelined-SAR ADC with analog–digital corrections in 28-nm CMOS AT Ramkaj, JCP Ramos, MJM Pelgrom, MSJ Steyaert, M Verhelst, ... IEEE Journal of Solid-State Circuits 55 (6), 1553-1564, 2020 | 64 | 2020 |
A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS AT Ramkaj, MSJ Steyaert, F Tavernier IEEE Solid-State Circuits Letters 2 (9), 167 - 170, 2019 | 50 | 2019 |
3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS A Ramkaj, JCP Ramos, Y Lyu, M Strackx, JMM Pelgrom, M Steyaert, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 62-64, 2019 | 32 | 2019 |
A 28 nm CMOS triple-latch feed-forward dynamic comparator with< 27 ps/1 V and< 70 ps/0.6 V delay at 5 mV-sensitivity AT Ramkaj, MJM Pelgrom, MSJ Steyaert, F Tavernier IEEE Transactions on Circuits and Systems I: Regular Papers 69 (11), 4404-4414, 2022 | 20 | 2022 |
Fast switch bootstrapping for GS/s high-resolution analog-to-digital converter A Ramkaj, F Tavernier, M Steyaert 2015 11th Conference on Ph. D. Research in Microelectronics and Electronics …, 2015 | 14 | 2015 |
An 11 GHz dual-sided self-calibrating dynamic comparator in 28 nm CMOS A Ramkaj, M Strackx, M Steyaert, F Tavernier Electronics 8 (1), 13, 2018 | 12 | 2018 |
A 36.4 dB SNDR@ 5GHz 1.25 GS/s 7b 3.56 mW single-channel SAR ADC in 28nm bulk CMOS A Ramkaj, M Strackx, M Steyaert, F Tavernier ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 167-170, 2017 | 11 | 2017 |
A 30GHz-BW<-57dB-IM3 direct RF receiver analog front end in 16nm FinFET A Ramkaj, A Cantoni, G Manganaro, S Devarajan, M Steyaert, F Tavernier 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 8 | 2022 |
Bootstrapped switch A Ramkaj, MH Perrott, BS Haroun, B Murmann US Patent App. 18/296,649, 2024 | 6 | 2024 |
In the pursuit of the optimal accuracy–speed–power analog-to-digital converter architecture: A mathematical framework A Ramkaj, MJM Pelgrom, MSJ Steyaert, F Tavernier IEEE Solid-State Circuits Magazine 14 (1), 45-53, 2022 | 6 | 2022 |
High‐gain and power‐efficient dynamic amplifier for pipelined SAR ADCs Y Lyu, A Ramkaj, F Tavernier Electronics Letters 53 (23), 1510-1512, 2017 | 6 | 2017 |
A 1024-Channel 268-nW/Pixel 36× 36 µm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces M Jang, M Hays, WH Yu, C Lee, P Caragiulo, AT Ramkaj, P Wang, ... IEEE Journal of Solid-State Circuits 59 (4), 1123-1136, 2023 | 5 | 2023 |
Analysis and Design of High-Speed Successive Approximation Register ADCs–M. Sc AT Ramkaj Thesis, 2014 | 5 | 2014 |
Multi-Gigahertz Nyquist Analog-to-Digital Converters: Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies AT Ramkaj, MJM Pelgrom, MSJ Steyaert, F Tavernier Springer, 2023 | 2 | 2023 |
Multi-Gigahertz Nyquist Analog-to-Digital Converters AT Ramkaj, MJM Pelgrom, MSJ Steyaert, F Tavernier | 2 | |
Front-end for receivers with rf sampling adcs A Ramkaj, G Manganaro, F Tavernier, S Devarajan US Patent App. 17/903,970, 2023 | 1 | 2023 |
Ultrahigh-Speed High-Sensitivity Dynamic Comparator AT Ramkaj, MJM Pelgrom, MSJ Steyaert, F Tavernier Multi-Gigahertz Nyquist Analog-to-Digital Converters: Architecture and …, 2022 | 1 | 2022 |
A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS P Caragiulo, A Ramkaj, A Arbabian, B Murmann ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 1 | 2022 |
Amplifiers for rf adcs G Manganaro, A Ramkaj, F Tavernier US Patent 11,437,963, 2022 | 1 | 2022 |