| Ai edge devices using computing-in-memory and processing-in-sensor: from system to device TH Hsu, YC Chiu, WC Wei, YC Lo, CC Lo, RS Liu, KT Tang, MF Chang, ... 2019 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2019 | 36 | 2019 |
| Physically tightly coupled, logically loosely coupled, near-memory BNN accelerator (PTLL-BNN) YC Lo, YC Kuo, YS Chang, JH Huang, JS Wu, WC Ting, TH Wen, RS Liu ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 8 | 2019 |
| FlexNet: Neural networks with inherent inference-time bitwidth flexibility YS Hsiao, YC Lo, RS Liu ACM Student Research Competition Silver Award at International Symposium on …, 2018 | 7 | 2018 |
| Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips YC Lo, B Li, S Park, K Shin, TY Ho Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 5 | 2021 |
| ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators YC Lo, CC Yeh, JS Wu, CC Wang, YC Tsai, WC Ting, RS Liu Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 4 | 2022 |
| DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout RS Liu, YC Lo, YC Luo, CY Shen, CJ Lee 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2018 | 4 | 2018 |
| Block and Subword-Scaling Floating-Point (BSFP): An Efficient Non-Uniform Quantization For Low Precision Inference YC Lo, TK Lee, RS Liu The Eleventh International Conference on Learning Representations (ICLR), 2023 | 3 | 2023 |
| LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks YC Lo, YC Tsai, RS Liu IEEE Computer Architecture Letters, 2023 | 1 | 2023 |
| Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference YC Lo, RS Liu 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 1 | 2023 |
| Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture YC Lo, RS Liu 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 1 | 2023 |
| Processor for neural network operation Yun-Chen LO, Yu-Chun KUO, Yun-Sheng CHANG, Jian-Hao HUANG, Jun-Shen WU, Wen ... US Patent App. 17/108,470, 2021 | 1* | 2021 |
| Neural network method, system, and computer program product with inference-time bitwidth flexibility LO Yun-Chen, YS HSIAO, RS Liu US Patent App. 16/545,181, 2020 | 1 | 2020 |
| Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators CC Wang, YC Lo, JS Wu, YC Tsai, CC Chang, TW Hsu, MW Chu, CY Lai, ... 2023 IEEE 41st International Conference on Computer Design (ICCD), 515-522, 2023 | | 2023 |
| BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed! YC Lo, CC Wang, RS Liu 2023 IEEE 41st International Conference on Computer Design (ICCD), 531-534, 2023 | | 2023 |
| Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs YC Lo, RS Liu IEEE/ACM International Symposium on Microarchitecture (MICRO-56), 1002-1015, 2023 | | 2023 |
Ren-Shuo LiuNational Tsing Hua UniversityVerified email at ee.nthu.edu.tw
