Luigi Pantisano
Luigi Pantisano
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Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics
A Kerber, E Cartier, L Pantisano, R Degraeve, T Kauerauf, Y Kim, A Hou, ...
IEEE Electron Device Letters 24 (2), 87-89, 2003
Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions
M Houssa, L Pantisano, LÅ Ragnarsson, R Degraeve, T Schram, ...
Materials Science and Engineering: R: Reports 51 (4-6), 37-85, 2006
Evidences of oxygen-mediated resistive-switching mechanism in TiN\HfO2\Pt cells
L Goux, P Czarnecki, YY Chen, L Pantisano, XP Wang, R Degraeve, ...
Applied Physics Letters 97 (24), 2010
Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/gate dielectrics
A Kerber, E Cartier, L Pantisano, M Rosmeulen, R Degraeve, T Kauerauf, ...
2003 IEEE International Reliability Physics Symposium Proceedings, 2003 …, 2003
Passivation and interface state density of -based/polycrystalline-Si gate stacks
RJ Carter, E Cartier, A Kerber, L Pantisano, T Schram, S De Gendt, ...
Applied physics letters 83 (3), 533-535, 2003
On the gradual unipolar and bipolar resistive switching of TiN\HfO2\Pt memory systems
L Goux, YY Chen, L Pantisano, XP Wang, G Groeseneken, M Jurczak, ...
Electrochemical and Solid-State Letters 13 (6), G54, 2010
Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
J Mitard, B De Jaeger, FE Leys, G Hellings, K Martens, G Eneman, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Noise in Drain and Gate Current of MOSFETs With High- Gate Stacks
P Magnone, F Crupi, G Giusi, C Pace, E Simoen, C Claeys, L Pantisano, ...
IEEE Transactions on Device and Materials Reliability 9 (2), 180-189, 2009
Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness
E Simoen, A Mercha, L Pantisano, C Claeys, E Young
IEEE transactions on electron devices 51 (5), 780-784, 2004
On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices
J Westlinder, T Schram, L Pantisano, E Cartier, A Kerber, GS Lujan, ...
IEEE Electron Device Letters 24 (9), 550-552, 2003
Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/gate stacks with TiN electrodes
A Kerber, E Cartier, R Degraeve, PJ Roussel, L Pantisano, T Kauerauf, ...
IEEE Transactions on Electron Devices 50 (5), 1261-1269, 2003
Intrinsic switching behavior in HfO2 RRAM by fast electrical measurements on novel 2R test structures
A Fantini, DJ Wouters, R Degraeve, L Goux, L Pantisano, G Kar, YY Chen, ...
2012 4th IEEE International Memory Workshop, 1-4, 2012
Effect of bulk trap density on HfO/sub 2/reliability and yield
R Degraeve, A Kerber, P Roussell, E Cartier, T Kauerauf, L Pantisano, ...
IEEE International Electron Devices Meeting 2003, 38.5. 1-38.5. 4, 2003
Estimation of fixed charge densities in hafnium-silicate gate dielectrics
VS Kaushik, BJ O'Sullivan, G Pourtois, N Van Hoornick, A Delabie, ...
IEEE Transactions on Electron Devices 53 (10), 2627-2633, 2006
Reliability screening of high-k dielectrics based on voltage ramp stress
A Kerber, L Pantisano, A Veloso, G Groeseneken, M Kerber
Microelectronics reliability 47 (4-5), 513-517, 2007
A study of relaxation current in high-/spl kappa/dielectric stacks
Z Xu, L Pantisano, A Kerber, R Degraeve, E Cartier, S De Gendt, M Heyns, ...
IEEE Transactions on Electron Devices 51 (3), 402-408, 2004
Impact of EOT scaling down to 0.85 nm on 70nm Ge-pFETs technology with STI
J Mitard, C Shea, B DeJaeger, A Pristera, G Wang, M Houssa, G Eneman, ...
2009 Symposium on VLSI Technology, 82-83, 2009
Towards understanding degradation and breakdown of SiO2/high-k stacks
T Kauerauf, R Degraeve, E Cartier, B Govoreanu, P Blomme, B Kaczer, ...
Digest. International Electron Devices Meeting,, 521-524, 2002
Stress-induced positive charge in Hf-based gate dielectrics: Impact on device performance and a framework for the defect
CZ Zhao, JF Zhang, MH Chang, AR Peaker, S Hall, G Groeseneken, ...
IEEE Transactions on Electron Devices 55 (7), 1647-1656, 2008
Performance comparison of sub 1 nm sputtered TiN/HfO~ 2 nMOS and pMOSFETs
W Tsai, LA Ragnarsson, L Pantisano, PJ Chen, B Onsia, T Schram, ...
International Electron Devices Meeting, 311-314, 2003
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