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Jian Zhang
Jian Zhang
HiSilicon, EPFL
Verified email at epfl.ch
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Year
Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs
M De Marchi, D Sacchetto, S Frache, J Zhang, PE Gaillardon, Y Leblebici, ...
Electron Devices Meeting (IEDM), 2012 IEEE International, 8.4. 1-8.4. 4, 2012
3162012
Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs
M De Marchi, J Zhang, S Frache, D Sacchetto, PE Gaillardon, Y Leblebici, ...
IEEE Electron Device Letters 35 (8), 880-882, 2014
1222014
Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity
M De Marchi, D Sacchetto, J Zhang, S Frache, PE Gaillardon, Y Leblebici, ...
IEEE Transactions on Nanotechnology 13 (6), 1029-1038, 2014
1062014
A charge-based model for long-channel cylindrical surrounding-gate MOSFETs from intrinsic channel to heavily doped body
F Liu, J He, L Zhang, J Zhang, J Hu, C Ma, M Chan
IEEE transactions on electron devices 55 (8), 2187-2194, 2008
982008
Configurable circuits featuring dual-threshold-voltage design with three-independent-gate silicon nanowire FETs
J Zhang, X Tang, PE Gaillardon, G De Micheli
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2851-2861, 2014
922014
Polarity-controllable silicon nanowire transistors with dual threshold voltages
J Zhang, M De Marchi, D Sacchetto, PE Gaillardon, Y Leblebici, ...
IEEE Transactions on Electron Devices 61 (11), 3654-3660, 2014
842014
A Schottky-barrier silicon FinFET with 6.0 mV/dec subthreshold slope over 5 decades of current
J Zhang, M De Marchi, PE Gaillardon, G De Micheli
Electron Devices Meeting (IEDM), 2014 IEEE International, 13.4. 1-13.4. 4, 2014
732014
Advanced system on a chip design based on controllable-polarity FETs
PE Gaillardon, L Amaru, J Zhang, G De Micheli
Proceedings of the conference on Design, Automation & Test in Europe, 235, 2014
512014
Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs
J Zhang, PE Gaillardon, G De Micheli
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, 2111-2114, 2013
502013
A non-charge-sheet analytic model for symmetric double-gate MOSFETs with smooth transition between partially and fully depleted operation modes
F Liu, J He, J Zhang, Y Chen, M Chan
IEEE transactions on electron devices 55 (12), 3494-3502, 2008
472008
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors
L Amar˙, PE Gaillardon, J Zhang, G De Micheli
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (10), 672-676, 2013
432013
A carrier-based approach for compact modeling of the long-channel undoped symmetric double-gate MOSFETs
J He, F Liu, J Zhang, J Feng, J Hu, S Yang, M Chan
IEEE transactions on electron devices 54 (5), 1203-1209, 2007
432007
An approximate carrier-based compact model for fully depleted surrounding-gate MOSFETs with a finite doping body
J He, F Liu, W Bian, J Feng, J Zhang, X Zhang
Semiconductor science and technology 22 (6), 671, 2007
332007
Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to strong-inversion regions
F Liu, L Zhang, J Zhang, J He, M Chan
Semiconductor Science and Technology 24 (8), 085005, 2009
282009
A charge-based compact model for predicting the current–voltage and capacitance–voltage characteristics of heavily doped cylindrical surrounding-gate MOSFETs
F Liu, J Zhang, F He, F Liu, L Zhang, M Chan
Solid-State Electronics 53 (1), 49-53, 2009
272009
TSPC flip-flop circuit design with three-independent-gate silicon nanowire FETs
X Tang, J Zhang, PE Gaillardon, G De Micheli
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1660-1663, 2014
212014
An analytic model for nanowire MOSFETs with Ge/Si core/shell structure
L Zhang, J He, J Zhang, F Liu, Y Fu, Y Song, X Zhang
IEEE Transactions on Electron Devices 55 (11), 2907-2917, 2008
202008
On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET
J Zhang, J Trommer, WM Weber, PE Gaillardon, G De Micheli
IEEE Journal of the Electron Devices Society 3 (6), 452-456, 2015
182015
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors
S Bobba, PE Gaillardon, J Zhang, M De Marchi, D Sacchetto, Y Leblebici, ...
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCHá…, 2012
182012
FinFET: From compact modeling to circuit performance
F He, X Zhou, C Ma, J Zhang, Z Liu, W Wu, X Zhang, L Zhang
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE Internationalá…, 2010
172010
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