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Mohammad Najmzadeh, Ph.D.
Mohammad Najmzadeh, Ph.D.
Verified email at intel.com - Homepage
Title
Cited by
Cited by
Year
MoS2 Heterojunctions by Thickness Modulation
M Tosun, D Fu, SB Desai, C Ko, JS Kang, DH Lien, M Najmzadeh, ...
Scientific reports 5, 2015
912015
The high-mobility bended n-channel silicon nanowire transistor
KE Moselund, M Najmzadeh, P Dobrosz, SH Olsen, D Bouvet, ...
IEEE transactions on electron devices 57 (4), 866-876, 2010
472010
A silicon straight tube fluid density sensor
M Najmzadeh, S Haasl, P Enoksson
Journal of Micromechanics and Microengineering 17 (8), 1657-1663, 2007
312007
Quantum well InAs/AlSb/GaSb vertical Tunnel FET with HSQ mechanical support
Y Zeng, CI Kuo, C Hsu, M Najmzadeh, A Sachid, R Kapadia, C Yeung, ...
IEEE Transactions on Nanotechnology 14, 580 - 584, 2015
262015
Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs
M Najmzadeh, L De Michielis, D Bouvet, P Dobrosz, S Olsen, AM Ionescu
Microelectronic engineering 87 (5-8), 1561-1565, 2010
242010
Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs
M Najmzadeh, L De Michielis, D Bouvet, P Dobrosz, S Olsen, AM Ionescu
MNE 2009, Ghent, Belgium, 2009
242009
Multilayer ReS2 lateral p-n homojunction for photoemission and photodetection
M Najmzadeh, C Ko, K Wu, S Tongay, J Wu
Applied Physics Express 9, 055201, 2016
212016
Investigation of oxidation-induced strain in a top-down Si nanowire platform
M Najmzadeh, D Bouvet, P Dobrosz, S Olsen, AM Ionescu
Microelectronic engineering 86 (7-9), 1961-1964, 2009
212009
Investigation of oxidation-induced strain in a top-down Si nanowire platform
M Najmzadeh, D Bouvet, P Dobrosz, O Sarah, MA Ionescu
INFOS 2009 (biennial), Cambridge, UK, 2009
212009
Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain
M Najmzadeh, D Bouvet, W Grabinski, JM Sallese, AM Ionescu
Solid-State Electronics 74, 114-120, 2012
192012
Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm
M Najmzadeh, M Berthomé, JM Sallese, W Grabinski, AM Ionescu
Solid-State Electronics (selected IEEE ULIS 2013; Warwick) 98, 55-62, 2014
142014
Asymmetrically strained all-silicon multi-gate n-Tunnel FETs
M Najmzadeh, K Boucart, W Riess, AM Ionescu
Solid-State Electronics 54 (9), 935-941, 2010
132010
Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs
M Najmzadeh, JM Sallese, M Berthomé, W Grabinski, AM Ionescu
IEEE Transactions on Electron Devices 59 (12), 3519-3526, 2012
112012
Multi-gate buckled self-aligned dual Si nanowire MOSFETs on bulk Si for high electron mobility (Front Cover)
M Najmzadeh, Y Tsuchiya, D Bouvet, W Grabinski, AM Ionescu
IEEE Transactions on Nanotechnology 11 (5), C1, 2012
9*2012
Multi-gate buckled self-aligned dual Si nanowire MOSFETs on bulk Si for high electron mobility
M Najmzadeh, Y Tsuchiya, D Bouvet, W Grabinski, AM Ionescu
IEEE Transactions on Nanotechnology 11 (5), 902-906, 2012
92012
Accumulation-mode GAA Si NW nFET with sub-5 nm cross-section and high uniaxial tensile strain
M Najmzadeh, D Bouvet, W Grabinski, AM Ionescu
2011 Proceedings of the European Solid-State Device Research Conference …, 2011
92011
2D MOSFET operation of a fully-depleted bulk MoS2 at quasi-flatband back-gate
M Najmzadeh, JP Duarte, S Khandelwal, Y Zeng, C Hu
IEEE DRC 2015 (the 73rd IEEE Device Research Conf.; Ohio State University …, 2015
72015
Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling
M Najmzadeh, D Bouvet, W Grabinski, AM Ionescu
2011 International Semiconductor Device Research Symposium (ISDRS), 1-2, 2011
72011
Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs
M Najmzadeh, D Bouvet, W Grabinski, AM Ionescu
69th Device Research Conference, 145-146, 2011
62011
Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic
M Najmzadeh, Y Tsuchiya, D Bouvet, W Grabinski, AM Ionescu
Microelectronic Engineering 110, 278-281, 2013
5*2013
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