A neutral netlist of 10 combinational circuits and a targeted translator in FORTRAN F Brglez, H Fujiwara IEEE, Proc. Int. Symp. on Circuits and Systems (ISCAS'85), pp. 663-698, 1985 | 1917* | 1985 |

On the acceleration of test generation algorithms H Fujiwara, T Shimono IEEE Transactions on Computers, 1137-1144, 1983 | 1029 | 1983 |

Logic Testing and Design for Testability H Fujiwara MIT Press, 1985 | 599 | 1985 |

The complexity of fault detection problems for combinational circuits H Fujiwara, S Toida IEEE Transactions on computers 31 (6), 555-560, 1982 | 181* | 1982 |

A design of programmable logic arrays with universal tests H Fujiwara, K Kinoshita Joint Special Issue on Design for Testability, IEEE Trans. on Computers …, 1981 | 144 | 1981 |

FAN: A Fanout-Oriented Test Pattern Generation Algorithm H Fujiwara IEEE International Symposium on Circuits and Systems, 671-674, 1985 | 113 | 1985 |

Implementing a built-in self-test PLA design R Treuer, H Fujiwara, VK Agarwal IEEE Design & Test of Computers 2 (2), 37-48, 1985 | 91 | 1985 |

A test methodology for interconnect structures of LUT-based FPGAs H Michinishi, T Yokohira, T Okamoto, T Inoue, H Fujiwara Proceedings of the Fifth Asian Test Symposium (ATS'96), 68-74, 1996 | 88 | 1996 |

Parity-scan design to reduce the cost of test application H Fujiwara, A Yamamoto IEEE transactions on computer-aided design of integrated circuits and …, 1993 | 82 | 1993 |

Universal fault diagnosis for lookup table FPGAs T Inoue, S Miyazaki, H Fujiwara IEEE Design & Test of Computers 15 (1), 39-44, 1998 | 79 | 1998 |

A new PLA design for universal testability H Fujiwara IEEE transactions on computers 100 (8), 745-750, 1984 | 75 | 1984 |

Efficient test solutions for core-based designs E Larsson Introduction to Advanced System-on-Chip Test Design and Optimization, 215-251, 2005 | 72 | 2005 |

Universal test complexity of field-programmable gate arrays T Inoue, H Fujiwara, H Michinishi, T Yokohira, T Okamoto Proceedings of the Fourth Asian Test Symposium, 259-265, 1995 | 71 | 1995 |

SPIRIT: A highly robust combinational test generation algorithm E Gizdarski, H Fujiwara IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002 | 68 | 2002 |

Computational complexity of controllability/observability problems for combinational circuits H Fujiwara IEEE Transactions on Computers 39 (6), 762-767, 1990 | 67 | 1990 |

Reconfigured scan forest for test application cost, test data volume, and test power reduction D Xiang, K Li, J Sun, H Fujiwara IEEE Transactions on Computers 56 (4), 557-562, 2007 | 65 | 2007 |

Easily testable sequential machines with extra inputs H Fujiwara, Y Nagao, T Sasao, K Kinoshita IEEE Transactions on Computers 100 (8), 821-826, 1975 | 62 | 1975 |

An optimal time expansion model based on combinational ATPG for RT level circuits T Inoue, T Hosokawa, T Mihara, H Fujiwara Proceedings Seventh Asian Test Symposium (ATS'98)(Cat. No. 98TB100259), 190-197, 1998 | 59 | 1998 |

On the computational complexity of system diagnosis H Fujiwara, K Kinoshita IEEE Transactions on Computers 100 (27), 1978 | 59 | 1978 |

An efficient scan tree design for test time reduction. Y Bonhomme, T Yoneda, H Fujiwara, P Girard ETS, 174-179, 2004 | 55 | 2004 |