| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 771 | 2017 |
| Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond CC Liu, E Franke, Y Mignot, R Xie, CW Yeung, J Zhang, C Chi, C Zhang, ... Nature Electronics 1 (10), 562-569, 2018 | 103 | 2018 |
| Tungsten and cobalt metallization: A material study for MOL local interconnects V Kamineni, M Raymond, S Siddiqui, F Mont, S Tsai, C Niu, A Labonte, ... 2016 IEEE International Interconnect Technology Conference/Advanced …, 2016 | 57 | 2016 |
| EUV patterning successes and frontiers N Felix, D Corliss, K Petrillo, N Saulnier, Y Xu, L Meli, H Tang, A De Silva, ... Extreme Ultraviolet (EUV) Lithography VII 9776, 480-486, 2016 | 39 | 2016 |
| BEOL process integration for the 7 nm technology node T Standaert, G Beique, HC Chen, ST Chen, B Hamieh, J Lee, ... 2016 IEEE international interconnect technology conference/advanced …, 2016 | 37 | 2016 |
| SiCOH hardmask with graded transition layers MS Angyal, YS Loquet, YA Mignot, SV Nguyen, M Sankarapandian, ... US Patent 8,927,442, 2015 | 29 | 2015 |
| Surface treatment of wire bonding metal pads S Alberici, D Coulon, P Joubin, Y Mignot, L Oggioni, P Petruzza, D Piumi, ... Microelectronic engineering 70 (2-4), 558-565, 2003 | 25 | 2003 |
| SiARC removal with plasma etch and fluorinated wet chemical solution combination Y Mignot, BC Peethala, S Siddiqui US Patent 9,508,560, 2016 | 24 | 2016 |
| Integration of super via structure in BEOL R Bao, J Lee, Y Mignot, H Shobha, J Wang, Y Xu US Patent App. 10/020,254, 2018 | 22* | 2018 |
| Advanced interconnect with air gap JH Zhang, Y Mignot, LA Clevenger, C Radens, RS Wise, XU Yiheng, ... US Patent App. 14/098,286, 2015 | 21 | 2015 |
| Trench interconnect having reduced fringe capacitance JH Zhang, HC Chen, LA Clevenger, Y Mignot, C Radens, RS Wise, ... US Patent 9,214,429, 2015 | 20 | 2015 |
| Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs SD Burns, LA Clevenger, ME Colburn, SK Kanakasabapathy, YAM Mignot, ... US Patent 9,991,156, 2018 | 19 | 2018 |
| Integration of super via structure in BEOL R Bao, J Lee, Y Mignot, H Shobha, J Wang, Y Xu US Patent 10,020,254, 2018 | 17 | 2018 |
| Defect detection strategies and process partitioning for SE EUV patterning L Meli, K Petrillo, A De Silva, J Arnold, N Felix, C Robinson, B Briggs, ... Extreme Ultraviolet (EUV) Lithography IX 10583, 87-103, 2018 | 17 | 2018 |
| 56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme Y Loquet, Y Mignot, C Waskiewicz, JHC Chen, M Sankarapandian, ... Microelectronic Engineering 107, 138-144, 2013 | 17 | 2013 |
| Selective gas etching for self-aligned pattern transfer JC Arnold, SD Burns, YAM MIGNOT, Y Xu US Patent 10,032,632, 2018 | 15 | 2018 |
| Method for residue-free block pattern transfer onto metal interconnects for air gap formation J Lee, Y Mignot, BC Peethala US Patent 9,390,967, 2016 | 15 | 2016 |
| Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP) Y Feurprier, K Lutker-Lee, V Rastogi, H Matsumoto, Y Chiba, A Metz, ... Advanced Etch Technology for Nanopatterning IV 9428, 57-66, 2015 | 15 | 2015 |
| Via formation using sidewall image transfer process to define lateral dimension ST Chen, C Chi, C Liu, SM Mignot, YA Mignot, HK Shobha, TA Spooner, ... US Patent 9,490,168, 2016 | 14 | 2016 |
| Integration of super via structure in BEOL R Bao, J Lee, Y Mignot, H Shobha, J Wang, Y Xu US Patent 10,020,255, 2018 | 13 | 2018 |
Chi-Chun LiuIBM ResearchVerified email at us.ibm.com
