Feasibility of coaxial through silicon via 3D integration S Adamshick, D Coolbaugh, M Liehr Electronics letters 49 (16), 1028-1030, 2013 | 35 | 2013 |
Experimental characterization of coaxial through silicon vias for 3D integration S Adamshick, D Coolbaugh, M Liehr Microelectronics Journal 46 (5), 377-382, 2015 | 16 | 2015 |
High frequency electrical characterization of 3D signal/ground through silicon vias S Adamshick, R Carroll, M Rao, D La Tuplie, S Kruger, J Burke, M Liehr Progress In Electromagnetics Research Letters 47, 71-75, 2014 | 6 | 2014 |
Antenna on Chip Design Utilizing 3D Integration for Mixed Signal Applications S Adamshick, A Johnson, K Moriarty, W Tremblay, J Burke 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017 | 4 | 2017 |
A novel low loss 3D system-in-package approach for 60GHz antenna on chip applications S Adamshick, SR Govindarajulu, EA Alwan 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems …, 2020 | 2 | 2020 |
Experimental characterisation of coaxial TSV transistor keep out zones S Adamshick, S Northrup, M Liehr Micro & Nano Letters 13 (10), 1457-1459, 2018 | 1 | 2018 |
Characterization of Rigid and Flexible 3D Printed Planar Antennas T Searles, AD Johnson, M Musiak, J Burke, S Adamshick 2019 IEEE International Flexible Electronics Technology Conference (IFETC), 1-5, 2019 | | 2019 |
Fabrication method for annular/shielded copper interconnects S Adamshick, J Burke, M Liehr Micro & Nano Letters 12 (5), 301-303, 2017 | | 2017 |
3D integration with coaxial through silicon vias S Adamshick State University of New York at Albany, 2015 | | 2015 |
Diffusion along triple junctions is this the pathway for narrow Cu conductor lines? JR Lloyd, S Adamshick, C Durcan, Y Kandel, IN Lund, BT McGowan, ... 2012 IEEE International Integrated Reliability Workshop Final Report, 151-153, 2012 | | 2012 |