Valerio Tenace
Valerio Tenace
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Pass-XNOR logic: A new logic style for PN junction based graphene circuits
V Tenace, A Calimera, E Macii, M Poncino
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
162014
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits
V Tenace, A Calimera, E Macii, M Poncino
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
132015
SAID: A supergate-aided logic synthesis flow for memristive crossbars
V Tenace, RG Rizzo, D Bhattacharjee, A Chattopadhyay, A Calimera
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 372-377, 2019
72019
Exploiting the expressive power of graphene reconfigurable gates via post-synthesis optimization
S Miryala, V Tenace, A Calimera, E Macii, M Poncino, L Amarú, ...
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 39-44, 2015
72015
Layer-wise compressive training for convolutional neural networks
M Grimaldi, V Tenace, A Calimera
Future Internet 11 (1), 7, 2019
62019
Quasi-adiabatic logic arrays for silicon and beyond-silicon energy-efficient ICs
V Tenace, A Calimera, E Macii, M Poncino
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (12), 1111-1115, 2016
62016
Ultra-low power circuits using graphene p–n junctions and adiabatic computing
S Miryala, V Tenace, A Calimera, E Macii, M Poncino
Microprocessors and Microsystems 39 (8), 962-972, 2015
52015
Multiplication by inference using classification trees: A case-study analysis
RG Rizzo, V Tenace, A Calimera
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
42018
Activation-kernel extraction through machine learning
V Tenace, A Calimera
2017 New Generation of CAS (NGCAS), 5-8, 2017
42017
NBTI effects on tree-like clock distribution networks
W Liu, S Miryala, V Tenace, A Calimera, E Macii, M Poncino
Proceedings of the great lakes symposium on VLSI, 279-282, 2012
42012
Quasi-exact logic functions through classification trees
V Tenace, A Calimera
Integration 63, 248-255, 2018
32018
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits
V Tenace, A Calimera, E Macii, M Poncino
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
32016
A Clinically Applicable Approach to the Classification of B-Cell Non-Hodgkin Lymphomas with Flow Cytometry and Machine Learning
V Gaidano, V Tenace, N Santoro, S Varvello, A Cignetti, G Prato, G Saglio, ...
Cancers 12 (6), 1684, 2020
22020
Energy-efficient convolutional neural networks via recurrent data reuse
L Mocerino, V Tenace, A Calimera
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 848-853, 2019
22019
Logic Synthesis of Pass-Gate Logic Circuits with Emerging Ambipolar Technologies
V Tenace, A Calimera, E Macii, M Poncino
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
22018
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits
V Tenace, A Calimera, E Macii, M Poncino
2014 10th Conference on Ph. D. Research in Microelectronics and Electronics …, 2014
22014
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits
V Tenace, A Calimera
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
12018
A compression-driven training framework for embedded deep neural networks
M Grimaldi, F Pugliese, V Tenace, A Calimera
Proceedings of the Workshop on INTelligent Embedded Systems Architectures …, 2018
12018
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture
V Tenace, A Calimera, E Macii, M Poncino
2016 International Great Lakes Symposium on VLSI (GLSVLSI), 145-150, 2016
12016
Row-based body-bias assignment for dynamic thermal clock-skew compensation
V Tenace, S Miryala, A Calimera, A Macii, E Macii, M Poncino
Microelectronics Journal 45 (5), 530-538, 2014
12014
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