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Pratik Marolia
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Year
A reconfigurable computing system based on a cache-coherent fabric
N Oliver, RR Sharma, S Chang, B Chitlur, E Garcia, J Grecco, A Grier, ...
2011 International Conference on Reconfigurable Computing and FPGAs, 80-85, 2011
772011
Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
MC Adler, C Chou, NC Crago, K Fleming, KD Glossop, A Jaleel, ...
US Patent 10,387,319, 2019
432019
Non-posted write transactions for a computer bus
RM Sankaran, DJ Harriman, SO Stalley, RH Vakharwala, I Agarwal, ...
US Patent App. 17/955,353, 2023
202023
System with programmable multi-context accelerator circuitry
UY Kakaiya, P Marolia, JD Fender, S Nadathur, N Chitlur, Y Yang, ...
US Patent App. 16/024,563, 2019
152019
Non-posted write transactions for a computer bus
RM Sankaran, DJ Harriman, SO Stalley, RH Vakharwala, I Agarwal, ...
US Patent 10,970,238, 2021
122021
Network interface for data transport in heterogeneous computing environments
PM Marolia, RM Sankaran, A Raj, N Jani, P Sarangam, RO Sharp
US Patent 11,025,544, 2021
112021
Methods and apparatus to provide user-level access authorization for cloud-based field-programmable gate arrays
S Subhaschandra, S Krishnan, B Thomas, P Marolia
US Patent 10,528,768, 2020
112020
Coherency tracking apparatus and method for an attached coprocessor or accelerator
P Marolia, R Sankaran
US Patent 11,379,236, 2022
102022
Shared accelerator memory systems and methods
S Kumar, D Koufaty, P Lantz, P Marolia, R Sankaran, K Koning
US Patent 10,817,441, 2020
102020
System, apparatus and method for increasing efficiency of link communications
P Marolia, R Sankaran, I Agarwal, N Paliwal
US Patent 11,201,838, 2021
82021
Securely exposing an accelerator to privileged system components
J Fender, UY Kakaiya, M Nair, B Morris, P Marolia
US Patent 10,762,244, 2020
62020
Systems and methods for isolating an accelerated function unit and/or an accelerated function context
S Nadathur, PM Marolia, HM Mitchel, JJ Grecco, UY Kakaiya, DA Munday
US Patent 11,307,925, 2022
42022
System, apparatus and method for accessing multiple address spaces via a virtualization device
SK Kumar, R Sankaran, UY Kakaiya, PM Marolia
US Patent App. 16/909,068, 2020
42020
Pasid based routing extension for scalable iov systems
P Marolia, S Kumar, R Sankaran, UY Kakaiya
US Patent App. 17/026,516, 2021
32021
Watermarking FPGA bitstream for IP protection
PM Marolia
32008
Method, system, and apparatus for a coherency task list to minimize cache snooping between cpu and fpga
SS Chang, PM Marolia
US Patent App. 15/089,467, 2017
22017
Accelerator controller hub
P Marolia, A Herdrich, R Sankaran, R Pal, D Puffer, S Sur, A Durg
US Patent App. 17/083,200, 2021
12021
Securely exposing an accelerator to privileged system components
J Fender, UY Kakaiya, M Nair, B Morris, P Marolia
US Patent App. 16/912,076, 2020
12020
Extending a root complex to encompass an external component
MK Nair, RM Sankaran, UY Kakaiya, Z Chai, DM Lee, PM Marolia
US Patent 10,789,370, 2020
12020
Method, apparatus, and system for low latency communication
PM Marolia, N Chitlur, SS Chang
US Patent App. 13/827,695, 2014
12014
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