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Bharan Giridhar
Bharan Giridhar
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Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores
D Fick, RG Dreslinski, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
2012 IEEE International Solid-State Circuits Conference, 190-192, 2012
1202012
A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution
S Bang, A Wang, B Giridhar, D Blaauw, D Sylvester
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
1132013
Exploring DRAM organizations for energy-efficient and resilient exascale memories
B Giridhar, M Cieslak, D Duggal, R Dreslinski, HM Chen, R Patti, B Hold, ...
Proceedings of the International Conference on High Performance Computing …, 2013
892013
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization
Y Lee, B Giridhar, Z Foo, D Sylvester, D Blaauw
2011 IEEE International Solid-State Circuits Conference, 46-48, 2011
672011
Integrated 3D-stacked server designs for increasing physical density of key-value stores
A Gutierrez, M Cieslak, B Giridhar, RG Dreslinski, L Ceze, T Mudge
Proceedings of the 19th international conference on Architectural support …, 2014
662014
A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes
Y Lee, B Giridhar, Z Foo, DS Sylvester, DB Blaauw
IEEE Journal of Solid-State Circuits (JSSC) 48 (10), 2511-2521, 2013
632013
Scaling towards kilo-core processors with asymmetric high-radix topologies
N Abeyratne, R Das, Q Li, K Sewell, B Giridhar, RG Dreslinski, D Blaauw, ...
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
632013
Scaling Towards Kilo-Core Processors with Asymmetric High-Radix Topologies
N Abeyratne, R Das, Q Li, K Sewell, B Giridhar, RG Dreslinski, D Blaauw, ...
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
632013
Centip3De: A cluster-based NTC architecture with 64 ARM Cortex-M3 cores in 3D stacked 130 nm CMOS
D Fick, RG Dreslinski, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
IEEE Journal of Solid-State Circuits 48 (1), 104-117, 2012
632012
Centip3De: A 64-Core, 3D Stacked, Near-Threshold System
R Dreslinski, D Fick, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, Y Lee, ...
IEEE Micro 33 (2), 8-16, 2013
552013
13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS
B Giridhar, N Pinckney, D Sylvester, D Blaauw
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
332014
A 1.07 tbit/s 128× 128 swizzle network for simd processors
S Satpathy, Z Foo, B Giridhar, R Dreslinski, D Sylvester, T Mudge, ...
2010 Symposium on VLSI Circuits, 81-82, 2010
282010
Shortstop: An on-chip fast supply boosting technique
N Pinckney, M Fojtik, B Giridhar, D Sylvester, D Blaauw
2013 Symposium on VLSI Circuits, C290-C291, 2013
272013
Centip3de: A many-core prototype exploring 3d integration and near-threshold computing
RG Dreslinski, D Fick, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
Communications of the ACM 56 (11), 97-104, 2013
132013
Reevaluating Fast Dual-Voltage Power Rail Switching Circuitry
RG Dreslinski, B Giridhar, N Pinckney, D Blaauw, D Sylvester, T Mudge
Workshop on Duplicating, Deconstructing and Debunking (WDDD), in conjunction …, 2012
102012
Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating
B Giridhar, M Fojtik, D Fick, D Sylvester, D Blaauw
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013
62013
Memory circuitry including read voltage boost
B Giridhar, DT Blaauw, DM Sylvester
US Patent 9,275,702, 2016
52016
Memory sense amplifier with multiple modes of operation
B Giridhar, DT Blaauw, DM Sylvester
US Patent 9,036,405, 2015
52015
Adaptive Robustness Tuning for High Performance Domino Logic
B Giridhar, D Fick, M Fojtik, S Satpathy, D Bull, D Sylvester, D Blaauw
VLSI Circuits (VLSIC), 2011 Symposium on, 190-191, 2011
12011
Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch
B Giridhar, S Cheema, GM Hess
US Patent 10,217,494, 2019
2019
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