Yun Liang
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Chronos: A timing analyzer for embedded software
X Li, Y Liang, T Mitra, A Roychoudhury
Science of Computer Programming 69 (1-3), 56-67, 2007
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs
X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
Timing analysis of concurrent programs running on shared cache multi-cores
Y Li, V Suhendra, Y Liang, T Mitra, A Roychoudhury
2009 30th IEEE Real-Time Systems Symposium, 57-67, 2009
Evaluating fast algorithms for convolutional neural networks on FPGAs
L Lu, Y Liang, Q Xiao, S Yan
2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017
Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on FPGAs
Q Xiao, Y Liang, L Lu, S Yan, YW Tai
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
Coordinated static and dynamic cache bypassing for GPUs
X Xie, Y Liang, Y Wang, G Sun, T Wang
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
C-LSTM: Enabling efficient LSTM using structured compression techniques on FPGAs
S Wang, Z Li, C Ding, B Yuan, Q Qiu, Y Wang, Y Liang
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
An efficient compiler framework for cache bypassing on GPUs
X Xie, Y Liang, G Sun, D Chen
Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference on …, 2013
High-level synthesis: productivity, performance, and software constraints
Y Liang, K Rupnow, Y Li, D Min, MN Do, D Chen
Journal of Electrical and Computer Engineering 2012, 2012
Efficient GPU spatial-temporal multitasking
Y Liang, HP Huynh, K Rupnow, RSM Goh, D Chen
IEEE Transactions on Parallel and Distributed Systems 26 (3), 748-760, 2014
Optimizing the mapreduce framework on intel xeon phi coprocessor
M Lu, L Zhang, HP Huynh, Z Ong, Y Liang, B He, RSM Goh, R Huynh
2013 IEEE International Conference on Big Data, 125-130, 2013
Improving high level synthesis optimization opportunity through polyhedral transformations
W Zuo, Y Liang, P Li, K Rupnow, D Chen, J Cong
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators
G Zhong, A Prakash, Y Liang, T Mitra, S Niar
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
Enabling coordinated register allocation and thread-level parallelism optimization for GPUs
X Xie, Y Liang, X Li, Y Wu, G Sun, T Wang, D Fan
2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015
Hi-fi playback: Tolerating position errors in shift operations of racetrack memory
C Zhang, G Sun, X Zhang, W Zhang, W Zhao, T Wang, Y Liang, Y Liu, ...
Proceedings of the 42nd Annual International Symposium on Computer …, 2015
An accurate GPU performance model for effective control flow divergence optimization
Y Liang, MT Satria, K Rupnow, D Chen
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
Scale-free sparse matrix-vector multiplication on many-core architectures
Y Liang, WT Tang, R Zhao, M Lu, HP Huynh, RSM Goh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
Instruction cache locking using temporal reuse profile
Y Liang, T Mitra
Proceedings of the 47th Design Automation Conference, 344-349, 2010
SpWA: An efficient sparse winograd convolutional neural networks accelerator on FPGAs
L Lu, Y Liang
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications
J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 430-437, 2017
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