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Joseph J. Nahas
Joseph J. Nahas
Visiting Professor, Department of Computer Science and Engineering, University of Notre Dame
Verified email at nd.edu
Title
Cited by
Cited by
Year
Nanomagnet logic: progress toward system-level integration
MT Niemier, GH Bernstein, G Csaba, A Dingler, XS Hu, S Kurtz, S Liu, ...
Journal of Physics: Condensed Matter 23 (49), 493202, 2011
2392011
A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers
TW Andre, JJ Nahas, CK Subramanian, BJ Garni, HS Lin, A Omair, ...
IEEE journal of solid-state circuits 40 (1), 301-309, 2005
2072005
Sense amplifier bias circuit for a memory having at least two distinct resistance states
JJ Nahas, TW Andre, BJ Garni
US Patent 6,700,814, 2004
2042004
Two-dimensional heterojunction interlayer tunneling field effect transistors (thin-TFETs)
MO Li, D Esseni, JJ Nahas, D Jena, HG Xing
IEEE Journal of the Electron Devices Society 3 (3), 200-207, 2015
1612015
A 0.18/spl mu/m 4 Mbit toggling MRAM
M Durlam, D Addie, J Akerman, B Butcher, P Brown, J Chan, M DeHerrera, ...
2004 International Conference on Integrated Circuit Design and Technology …, 2004
1522004
Analog circuit design using tunnel-FETs
B Sedighi, XS Hu, H Liu, JJ Nahas, M Niemier
IEEE transactions on circuits and systems I: regular papers 62 (1), 39-48, 2014
1372014
Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics
CK Subramanian, JJ Nahas
US Patent 6,944,052, 2005
1042005
Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits
X Yin, A Aziz, J Nahas, S Datta, S Gupta, M Niemier, XS Hu
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
882016
Demonstrated reliability of 4-Mb MRAM
J Akerman, P Brown, M DeHerrera, M Durlam, E Fuchs, D Gajewski, ...
IEEE Transactions on Device and Materials Reliability 4 (3), 428-435, 2004
822004
Migrating tasks between asymmetric computing elements of a multi-core processor
A Naveh, Y Yosef, E Weissmann, A Aggarwal, E Rotem, A Mendelson, ...
US Patent 10,185,566, 2019
76*2019
MRAM and methods for reading the MRAM
MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ...
US Patent 6,909,631, 2005
612005
Modeling and computer simulation of a microwave-to-dc energy conversion element
JJ Nahas
IEEE Transactions on Microwave Theory and Techniques 23 (12), 1030-1035, 1975
591975
Sense amplifier for a memory having at least two distinct resistance states
JJ Nahas, TW Andre, BJ Garni, CK Subramanian
US Patent 6,600,690, 2003
502003
Magnetic–electrical interface for nanomagnet logic
S Liu, XS Hu, JJ Nahas, MT Niemier, W Porod, GH Bernstein
IEEE transactions on nanotechnology 10 (4), 757-763, 2010
442010
MRAM having error correction code circuitry and method therefor
JJ Nahas
US Patent 7,370,260, 2008
382008
A 4Mb 0.18/spl mu/m 1T1MTJ Toggle MRAM memory
J Nahas, T Andre, C Subramanian, B Garni, H Lin, A Omair, W Martino
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004
362004
TFET-based cellular neural network architectures
I Palit, XS Hu, J Nahas, M Niemier
International Symposium on Low Power Electronics and Design (ISLPED), 236-241, 2013
322013
Memory having a precharge circuit and method therefor
CK Subramanian, TW Andre, JJ Nahas
US Patent 6,711,052, 2004
292004
A 180 Kbit embeddable MRAM memory module
JJ Nahas, TW Andre, B Garni, C Subramanian, H Lin, SM Alam, ...
IEEE Journal of solid-state circuits 43 (8), 1826-1834, 2008
272008
Nontraditional computation using beyond-CMOS tunneling devices
B Sedighi, XS Hu, JJ Nahas, M Niemier
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (4 …, 2014
262014
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Articles 1–20