Richard Michael Veras
Richard Michael Veras
Assistant Professor, University of Oklahoma
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RAIDR: Retention-aware intelligent DRAM refresh
J Liu, B Jaiyen, R Veras, O Mutlu
ACM SIGARCH Computer Architecture News 40 (3), 1-12, 2012
When polyhedral transformations meet SIMD code generation
M Kong, R Veras, K Stock, F Franchetti, LN Pouchet, P Sadayappan
Proceedings of the 34th ACM SIGPLAN conference on Programming language …, 2013
A stencil compiler for short-vector simd architectures
T Henretty, R Veras, F Franchetti, LN Pouchet, J Ramanujam, ...
Proceedings of the 27th international ACM conference on International …, 2013
SPIRAL: Extreme performance portability
F Franchetti, TM Low, DT Popovici, RM Veras, DG Spampinato, ...
Proceedings of the IEEE 106 (11), 1935-1968, 2018
Analytical cache modeling and tilesize optimization for tensor contractions
R Li, A Sukumaran-Rajam, R Veras, TM Low, F Rastello, A Rountev, ...
Proceedings of the International Conference for High Performance Computing …, 2019
Compilers, hands-off my hands-on optimizations
R Veras, DT Popovici, TM Low, F Franchetti
Proceedings of the 3rd Workshop on Programming Models for SIMD/Vector …, 2016
Capturing the expert: Generating fast matrix-multiply kernels with spiral
R Veras, F Franchetti
High Performance Computing for Computational Science--VECPAR 2014: 11th …, 2015
FLAMES2S: From abstraction to high performance
R Veras, J Monette, R Van de Geijn, ES Quintana-Ortí
Computer Science Department, University of Texas at Austin, 2008
A Scale-Free Structure for Power-Law Graphs
RM Veras, TM Low, F Franchetti
High Performance Extreme Computing Conference (HPEC), 2016 IEEE, 2016
Automating the Last-Mile for High Performance Dense Linear Algebra
RM Veras, TM Low, TM Smith, RA van de Geijn, F Franchetti
ArXiv e-prints, 2016
On large-scale matrix-matrix multiplication on compressed structures
SG Krishna, A Narasimhan, S Radhakrishnan, R Veras
2021 IEEE International Conference on Big Data (Big Data), 2976-2985, 2021
A domain-specific language and compiler for stencil computations on short-vector simd and gpu architectures
T Henretty, J Holewinski, R Veras, F Franchetti, LN Pouchet, ...
Compilers for Parallel Computing Workshop, 2013
Transforming linear algebra libraries: From abstraction to high performance
RM Veras, JS Monette, ES Quintana-Ort, RA van de Geijn
ACM Trans. Math. Soft, 0
Observe locally, classify globally: Using gnns to identify sparse matrix structure
K Abdelaal, R Veras
International Work-Conference on Artificial Neural Networks, 149-161, 2023
Reinforcement Learning for Graph Coloring: Understanding the Power and Limits of Non-Label Invariant Representations
C Cummins, R Veras
arXiv preprint arXiv:2401.12470, 2024
A Framework for Analyzing the Robustness of Graph Models
K Abdelaal, R Veras
2023 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2023
Using q-learning to select the best among functionally equivalent implementations
M Oever, LE Grimley, RM Veras
Proceedings of the 8th ACM SIGPLAN International Workshop on Libraries …, 2022
RAIDR: Retention-Aware Intelligent DRAM Refresh
B Jaiyen, J Liu, R Veras, O Mutlu
From High-Level Specification to High-Performance Code
Z Wang, M O’Boyle, PS Rawat, M Vaidya, A Sukumaran-Rajam, ...
Proceedings of the IEEE 106 (11), 2018
A scale-free structure for real world networks
RM Veras, F Franchetti
2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017
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