| Tpp: Transparent page placement for cxl-enabled tiered-memory HA Maruf, H Wang, A Dhanotia, J Weiner, N Agarwal, P Bhattacharya, ... Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 216 | 2023 |
| FastMP: a multi-core simulation methodology S Kanaujia, IE Papazian, J Chamberlain, J Baxter Workshop on Modeling, Benchmarking and Simulation, 2006 | 36 | 2006 |
| Who's afraid of uncorrectable bit errors? online recovery of flash errors with distributed redundancy A Tai, A Kryczka, SO Kanaujia, K Jamieson, MJ Freedman, A Cidon 2019 USENIX Annual Technical Conference (USENIX ATC 19), 977-992, 2019 | 29 | 2019 |
| Compression in cache design AR Adl-Tabatabai, AM Ghuloum, SO Kanaujia Proceedings of the 21st annual international conference on Supercomputing …, 2007 | 19 | 2007 |
| Extending sti for demanding hard-real-time systems B Welch, S Kanaujia, A Seetharam, D Thirumalai, AG Dean Proceedings of the 2003 international conference on Compilers, architecture …, 2003 | 16 | 2003 |
| Value cache in a computing system SO Kanaujia, K Saladi, N Vijayrao US Patent 9,990,301, 2018 | 11 | 2018 |
| Supporting demanding hard-real-time systems with STI BJ Welch, SO Kanaujia, A Seetharam, D Thirumalai, AG Dean IEEE Transactions on Computers 54 (10), 1188-1202, 2005 | 6 | 2005 |
| Live recovery of bit corruptions in datacenter storage systems A Tai, A Kryczka, S Kanaujia, C Petersen, M Antonov, M Waliji, ... arXiv preprint arXiv:1805.02790, 2018 | 5 | 2018 |
| Generate Video Using Software Thread Integration A Dean, S Kanaujia, B Welch Circuit Cellar, 10-19, 2003 | 1 | 2003 |
| Page cache and prefetch engine for external memory H Wang, CM Petersen, P Chauhan, A Dhanotia, SO Kanaujia US Patent App. 17/894,493, 2024 | | 2024 |
| Secure speculative execution of instructions H Wang, HD Dixit, SO Kanaujia US Patent 11,740,909, 2023 | | 2023 |
| Building Demanding Hard Real-Time Systems with Software Thread Integration S Kanaujia, B Welch, A Seetharam, D Thirumalai, A Dean | | |
