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Jaehoon Yu
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Year
Hiddenite: 4K-PE hidden network inference 4D-tensor engine exploiting on-chip model construction achieving 34.8-to-16.0 TOPS/W for CIFAR-100 and ImageNet
K Hirose, J Yu, K Ando, Y Okoshi, ÁL García-Arias, J Suzuki, T Van Chu, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
202022
Via-switch fpga: Highly dense mixed-grained reconfigurable architecture with overlay via-switch crossbars
H Ochi, K Yamaguchi, T Fujimoto, J Hotate, T Kishimoto, T Higashi, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
202018
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training
TY Cheng, Y Masuda, J Chen, J Yu, M Hashimoto
Integration 74, 19-31, 2020
162020
A speed-up scheme based on multiple-instance pruning for pedestrian detection using a support vector machine
J Yu, R Miyamoto, T Onoye
IEEE transactions on image processing 22 (12), 4752-4761, 2013
122013
Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension
K Kawamura, J Yu, D Okonogi, S Jimbo, G Inoue, A Hyodo, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 42-44, 2023
102023
Distilling knowledge for non-neural networks
S Fukui, J Yu, M Hashimoto
2019 Asia-Pacific Signal and Information Processing Association Annual …, 2019
102019
Minimizing power for neural network training with logarithm-approximate floating-point multiplier
TY Cheng, J Yu, M Hashimoto
2019 29th international symposium on power and timing modeling, optimization …, 2019
102019
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications
M Hashimoto, X Bai, N Banno, M Tada, T Sakamoto, J Yu, R Doi, Y Araki, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 502-504, 2020
82020
Sneak path free reconfiguration with minimized programming steps for via-switch crossbar-based FPGA
R Doi, J Yu, M Hashimoto
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
72019
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
K Mitsunari, J Yu, T Onoye, M Hashimoto
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2018
72018
A low-energy application specific instruction-set processor towards a low-computational lossless compression method for stimuli position data of artificial vision systems
T Sugiura, M Imai, J Yu, Y Takeuchi
Journal of Information Processing 25, 210-219, 2017
72017
A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis
T Sugiura, AU Khan, J Yu, Y Takeuchi, S Kameda, T Kamata, ...
2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), 432-435, 2016
72016
Influence of Numerical Precision on Machine Learning and Embedded Systems
K Mitsunari, J Yu
International Workshop on Smart Info-Media Systems in Asia, 164–169, 2016
72016
Implementation of AV streaming system using peer-to-peer communication
N Ishikawa, H Tsutsui, J Yu, T Izumi, H Ochi, Y Nakamura, T Komura, ...
2007 4th IEEE Consumer Communications and Networking Conference, 778-782, 2007
72007
Multicoated Supermasks Enhance Hidden Networks.
Y Okoshi, ÁL García-Arias, K Hirose, K Ando, K Kawamura, T Van Chu, ...
ICML, 17045-17055, 2022
62022
A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems
T Sugiura, J Yu, Y Takeuchi, M Imai
Biomedical Circuits and Systems Conference (BioCAS), 2015 IEEE, 97-100, 2015
62015
An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology
T Sugiura, S Nakatsuka, J Yu, Y Takeuchi, M Imai
2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings, 81-84, 2014
62014
Hidden-fold networks: Random recurrent residuals using sparse supermasks
ÁL García-Arias, M Hashimoto, M Motomura, J Yu
arXiv preprint arXiv:2111.12330, 2021
52021
Parallelism-flexible convolution core for sparse convolutional neural networks on FPGA
S Sombatsiri, S Shibata, Y Kobayashi, H Inoue, T Takenaka, T Hosomi, ...
IPSJ Transactions on System and LSI Design Methodology 12, 22-37, 2019
52019
Normalized channel features for accurate pedestrian detection
R Miyamoto, J Yu, T Onoye
2014 6th International Symposium on Communications, Control and Signal …, 2014
52014
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Articles 1–20