Mozhgan Mansuri
Cited by
Cited by
Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops
M Mansuri, D Liu, CKK Yang
Proceedings of the 27th European Solid-State Circuits Conference, 333-336, 2001
A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS
G Balamurugan, J Kennedy, G Banerjee, JE Jaussi, M Mansuri, ...
IEEE Journal of Solid-State Circuits 43 (4), 1010-1019, 2008
A 27-mW 3.6-gb/s I/O transceiver
KLJ Wong, H Hatamkhani, M Mansuri, CKK Yang
IEEE Journal of Solid-State Circuits 39 (4), 602-612, 2004
Jitter optimization based on phase-locked loop design parameters
M Mansuri, CK Ken
IEEE Journal of Solid-State Circuits 37 (11), 1375-1382, 2002
A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation
M Mansuri, CKK Yang
IEEE Journal of Solid-State Circuits 38 (11), 1804-1812, 2003
Systems, methods, and apparatuses for stacked memory
B Casper, R Mooney, D Dunning, M Mansuri, JE Jaussi
US Patent 8,612,809, 2013
Modeling and analysis of high-speed I/O links
G Balamurugan, B Casper, JE Jaussi, M Mansuri, F O'Mahony, J Kennedy
IEEE transactions on advanced packaging 32 (2), 237-247, 2009
A scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-lane parallel I/O in 32-nm CMOS
M Mansuri, JE Jaussi, JT Kennedy, TC Hsueh, S Shekhar, ...
IEEE Journal of solid-state circuits 48 (12), 3229-3242, 2013
A 4710 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
F O'Mahony, JE Jaussi, J Kennedy, G Balamurugan, M Mansuri, ...
IEEE journal of solid-state circuits 45 (12), 2828-2837, 2010
A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.
B Casper, J Jaussi, F O'Mahony, M Mansuri, K Canagasaby, J Kennedy, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
Strong Injection Locking in Low- LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver
S Shekhar, M Mansuri, F O'Mahony, G Balamurugan, JE Jaussi, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (8), 1818-1829, 2009
Future microprocessor interfaces: Analysis, design and optimization
B Casper, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, F O'Mahony, ...
2007 IEEE Custom Integrated Circuits Conference, 479-486, 2007
A 4–32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS
T Musah, JE Jaussi, G Balamurugan, S Hyvonen, TC Hsueh, G Keskin, ...
IEEE Journal of Solid-State Circuits 49 (12), 3079-3090, 2014
The future of electrical I/O for microprocessors
F O'Mahony, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, ...
2009 International Symposium on VLSI Design, Automation and Test, 31-34, 2009
A 27Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS
F O'Mahony, S Shekhar, M Mansuri, G Balamurugan, JE Jaussi, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
Low-power low-jitter on-chip clock generation
M Mansuri
University of California, Los Angeles, 2003
A programmable phase rotator based on time-modulated injection-locking
F O'Mahony, B Casper, M Mansuri, M Hossain
2010 Symposium on VLSI Circuits, 45-46, 2010
A low-jitter PLL and repeaterless clock distribution network for a 20Gb/s link
F O'Mahony, M Mansuri, B Casper, JE Jaussi, R Mooney
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 29, 2006
26.4 A 25.6 Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS
TC Hsueh, G Balamurugan, J Jaussi, S Hyvonen, J Kennedy, G Keskin, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
Design considerations for low-power receiver front-end in high-speed data links
S Shekhar, JE Jaussi, F O'Mahony, M Mansuri, B Casper
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-8, 2013
The system can't perform the operation now. Try again later.
Articles 1–20