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Andrew S. Cassidy
Andrew S. Cassidy
Research Staff Member, IBM Research
Adresse e-mail validée de us.ibm.com - Page d'accueil
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Année
A million spiking-neuron integrated circuit with a scalable communication network and interface
PA Merolla, JV Arthur, R Alvarez-Icaza, AS Cassidy, J Sawada, ...
Science 345 (6197), 668-673, 2014
31992014
Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip
F Akopyan, J Sawada, A Cassidy, R Alvarez-Icaza, J Arthur, P Merolla, ...
IEEE transactions on computer-aided design of integrated circuits and …, 2015
9912015
Backpropagation for energy-efficient neuromorphic computing
SK Esser, R Appuswamy, P Merolla, JV Arthur, DS Modha
Advances in neural information processing systems 28, 2015
9522015
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores
AS Cassidy, P Merolla, JV Arthur, SK Esser, B Jackson, R Alvarez-Icaza, ...
The 2013 International Joint Conference on Neural Networks (IJCNN), 1-10, 2013
3122013
Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores
SK Esser, A Andreopoulos, R Appuswamy, P Datta, D Barch, A Amir, ...
The 2013 International Joint Conference on Neural Networks (IJCNN), 1-10, 2013
1972013
Cognitive computing programming paradigm: a corelet language for composing networks of neurosynaptic cores
A Amir, P Datta, WP Risk, AS Cassidy, JA Kusnitz, SK Esser, ...
The 2013 International Joint Conference on Neural Networks (IJCNN), 1-10, 2013
1842013
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core
JV Arthur, PA Merolla, F Akopyan, R Alvarez, A Cassidy, S Chandra, ...
the 2012 international joint conference on Neural networks (IJCNN), 1-8, 2012
1842012
Conversion of artificial recurrent neural networks to spiking neural networks for low-power neuromorphic hardware
PU Diehl, G Zarrella, A Cassidy, BU Pedroni, E Neftci
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016
1822016
Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization
AS Cassidy, J Georgiou, AG Andreou
Neural Networks 45, 4-26, 2013
1152013
TrueNorth: Accelerating from zero to 64 million neurons in 10 years
MV DeBole, B Taba, A Amir, F Akopyan, A Andreopoulos, WP Risk, ...
Computer 52 (5), 20-29, 2019
932019
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications
J Sawada, F Akopyan, AS Cassidy, B Taba, MV Debole, P Datta, ...
SC'16: Proceedings of the International Conference for High Performance …, 2016
852016
Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with~ 100× speedup in time-to-solution and~ 100,000× reduction in energy-to-solution
AS Cassidy, R Alvarez-Icaza, F Akopyan, J Sawada, JV Arthur, ...
SC'14: Proceedings of the International Conference for High Performance …, 2014
852014
Design of a one million neuron single FPGA neuromorphic system for real-time multimodal scene analysis
A Cassidy, AG Andreou, J Georgiou
2011 45Th annual conference on information sciences and systems, 1-6, 2011
832011
Dynamical digital silicon neurons
A Cassidy, AG Andreou
2008 IEEE biomedical circuits and systems conference, 289-292, 2008
792008
Truehappiness: Neuromorphic emotion recognition on truenorth
PU Diehl, BU Pedroni, A Cassidy, P Merolla, E Neftci, G Zarrella
2016 international joint conference on neural networks (ijcnn), 4278-4285, 2016
782016
Beyond Amdahl's law: An objective function that links multiprocessor performance gains to delay and energy
AS Cassidy, AG Andreou
IEEE Transactions on Computers 61 (8), 1110-1126, 2011
782011
FPGA based silicon spiking neural array
A Cassidy, S Denham, P Kanold, A Andreou
2007 IEEE Biomedical Circuits and Systems Conference, 75-78, 2007
742007
Spiking optical flow for event-based sensors using IBM's TrueNorth neurosynaptic system
G Haessig, A Cassidy, R Alvarez, R Benosman, G Orchard
IEEE transactions on biomedical circuits and systems 12 (4), 860-870, 2018
552018
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
JM Paul, DE Thomas, AS Cassidy
ACM Transactions on Design Automation of Electronic Systems (TODAES) 10 (3 …, 2005
522005
Consolidating multiple neurosynaptic cores into one memory
RAI Rivera, JV Arthur, AS Cassidy, PA Merolla, DS Modha
US Patent 8,990,130, 2015
512015
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