Hans-Joachim Wunderlich
Hans-Joachim Wunderlich
Professor of Computer Science, University of Stuttgart
Verified email at informatik.uni-stuttgart.de - Homepage
TitleCited byYear
Minimized power consumption for scan-based BIST
S Gerstendörfer, HJ Wunderlich
Journal of Electronic Testing 16 (3), 203-212, 2000
4442000
Multiple distributions for biased random test patterns
HJ Wunderlich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990
2791990
Bit-flipping BIST
HJ Wunderlich, G Kiefer
Proceedings of International Conference on Computer Aided Design, 337-343, 1996
2711996
Power-aware testing and test strategies for low power devices
P Girard, N Nicolici, X Wen
Springer Science & Business Media, 2010
2262010
Pattern generation for a deterministic BIST scheme
S Hellebrand, B Reeb, S Tarnick, HJ Wunderlich
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
1831995
A modified clock scheme for a low power BIST test pattern generator
P Girard, L Guiller, C Landrault, S Pravossoudovitch, HJ Wunderlich
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 306-311, 2001
1782001
A mixed mode BIST scheme based on reseeding of folding counters
S Hellebrand, HG Liang, HJ Wunderlich
Journal of Electronic Testing 17 (3-4), 341-349, 2001
1712001
Low power serial built-in self-test
A Hertwig, HJ Wunderlich
Proceedings of IEEE European Test Workshop, 1998, 1998
1561998
Two-dimensional test data compression for scan-based deterministic BIST
HG Liang, S Hellebrand, HJ Wunderlich
Journal of Electronic Testing 18 (2), 159-170, 2002
1442002
PROTEST: a tool for probabilistic testability analysis
HJ Wunderlich
22nd ACM/IEEE Design Automation Conference, 204-211, 1985
1441985
An analytical approach to the partial scan problem
A Kunzmann, HJ Wunderlich
Journal of Electronic Testing 1 (2), 163-174, 1990
1381990
Self test using unequiprobable random patterns
HJ Wunderlich
1271987
Adaptive debug and diagnosis without fault dictionaries
S Holst, HJ Wunderlich
Journal of Electronic Testing 25 (4-5), 259-268, 2009
1102009
X-masking during logic BIST and its impact on defect coverage
Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ...
2004 International Conferce on Test, 442-451, 2004
1102004
Application of deterministic logic BIST on industrial circuits
G Kiefer, H Vranken, EJ Marinissen, HJ Wunderlich
Journal of Electronic Testing 17 (3-4), 351-362, 2001
1072001
An integrated built-in test and repair approach for memories with 2D redundancy
P Ohler, S Hellebrand, HJ Wunderlich
12th IEEE European Test Symposium (ETS'07), 91-96, 2007
1062007
Mixed-mode BIST using embedded processors
S Hellebrand, HJ Wunderlich, A Hertwig
On-line testing for VLSI, 127-138, 1998
1011998
Accumulator based deterministic BIST
R Dorsch, HJ Wunderlich
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
991998
Tailoring ATPG for embedded testing
R Dorsch, HJ Wunderlich
Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 530-537, 2001
962001
Deterministic BIST with multiple scan chains
G Kiefer, HJ Wunderlich
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
901998
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