| Design and performance of a main memory hardware data compressor M Kjelso, M Gooch, S Jones Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000 …, 1996 | 160 | 1996 |
| Gbit/s lossless data compression hardware JL Núñez, S Jones IEEE Transactions on very large scale integration (VLSI) systems 11 (3), 499-510, 2003 | 110 | 2003 |
| Performance evaluation of computer architectures with main memory data compression M Kjelsø, M Gooch, S Jones Journal of Systems Architecture 45 (8), 571-590, 1999 | 70 | 1999 |
| A 9-kbit associative memory for high-speed parallel processing applications SR Jones, IP Jalowiecki, SJ Hedge, RM Lea IEEE journal of solid-state circuits 23 (2), 543-548, 1988 | 56 | 1988 |
| Empirical study of memory-data: Characteristics and compressibility M Kjelsø, M Gooch, S Jones IEE Proceedings-Computers and Digital Techniques 145 (1), 63-67, 1998 | 46 | 1998 |
| High performance code compression architecture for the embedded ARM/Thumb processor XH Xu, CT Clarke, SR Jones Proceedings of the 1st Conference on Computing Frontiers, 451-456, 2004 | 43 | 2004 |
| VHDL: A Logic synthesis approach D Naylor, S Jones Springer Science & Business Media, 1997 | 41 | 1997 |
| 100 Mbit/s adaptive data compressor design using selectively shiftable content-addressable memory S Jones IEE Proceedings G (Circuits, Devices and Systems) 139 (4), 498-502, 1992 | 41 | 1992 |
| Word-based dynamic algorithms for data compression J Jiang, S Jones IEE Proceedings I (Communications, Speech and Vision) 139 (6), 582-586, 1992 | 40 | 1992 |
| Parallel design of arithmetic coding J Jiang, S Jones IEE Proceedings-Computers and Digital Techniques 141 (6), 327-333, 1994 | 34 | 1994 |
| Learning in linear systolic neural network engines: Analysis and implementation SR Jones, KM Sammut, J Hunter IEEE Transactions on Neural Networks 5 (4), 584-593, 1994 | 29 | 1994 |
| Data compression having more effective compression SR Jones, JLN Yanez US Patent 6,906,645, 2005 | 28 | 2005 |
| Asynchronous circuits based on multiple localised current-sensing completion detection E Grass, S Jones Proceedings Second Working Conference on Asynchronous Design Methodologies …, 1995 | 26 | 1995 |
| Memory management in flash-memory disks with data compression M KjelsØ, S Jones Memory Management: International Workshop IWMM 95 Kinross, UK, September 27 …, 1995 | 23 | 1995 |
| Toroidal neural network: Architecture and processor granularity issues S Jones, K Sammut, C Nielsen, J Staunstrup VLSI Design of Neural Networks, 229-254, 1991 | 23 | 1991 |
| Implementing nonlinear activation functions in neural network emulators KM Sammut, SR Jones Electronics letters 12 (27), 1037-1038, 1991 | 22 | 1991 |
| Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture S Jones IEE Proceedings E-Computers and Digital Techniques 135 (3), 165-172, 1988 | 22 | 1988 |
| X-MatchPRO: A ProASIC-based 200 Mbytes/s full-duplex lossless data compressor JL Nunez, C Feregrino, S Jones, S Bateman Field-Programmable Logic and Applications: 11th International Conference …, 2001 | 21 | 2001 |
| Targeted processor architectures for high-performance controller implementation S Jones, R Goodall, M Gooch Control Engineering Practice 6 (7), 867-878, 1998 | 21 | 1998 |
| Lossless data compression S Jones, JLN Yanez US Patent App. 10/208,006, 2004 | 19 | 2004 |
