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Yogesh S. Chauhan
Yogesh S. Chauhan
Fellow IEEE, FNAE, Professor-IIT Kanpur
Verified email at iitk.ac.in - Homepage
Title
Cited by
Cited by
Year
FinFET modeling for IC simulation and design: using the BSIM-CMG standard
YS Chauhan, DD Lu, S Venugopalan, S Khandelwal, JP Duarte, ...
Academic Press, 2015
1782015
Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance—Part II: Model validation
G Pahwa, T Dutta, A Agarwal, S Khandelwal, S Salahuddin, C Hu, ...
IEEE Transactions on Electron Devices 63 (12), 4986-4992, 2016
1732016
Analytical modeling of surface-potential and intrinsic charges in AlGaN/GaN HEMT devices
S Khandelwal, YS Chauhan, TA Fjeldly
IEEE Transactions on Electron Devices 59 (10), 2856-2860, 2012
1482012
BSIM—SPICE models enable FinFET and UTB IC designs
N Paydavosi, S Venugopalan, YS Chauhan, JP Duarte, S Jandhyala, ...
IEEE Access 1, 201-215, 2013
1272013
BSIM6: Analog and RF compact model for bulk MOSFET
YS Chauhan, S Venugopalan, MA Chalkiadaki, MAU Karim, H Agarwal, ...
IEEE Transactions on Electron Devices 61 (2), 234-244, 2013
1092013
Robust surface-potential-based compact model for GaN HEMT IC design
S Khandelwal, C Yadav, S Agnihotri, YS Chauhan, A Curutchet, T Zimmer, ...
IEEE Transactions on Electron Devices 60 (10), 3216-3222, 2013
1092013
Doping Strategies for Monolayer MoS2 via Surface Adsorption: A Systematic Study
P Rastogi, S Kumar, S Bhowmick, A Agarwal, YS Chauhan
The Journal of Physical Chemistry C 118 (51), 30309-30314, 2014
1052014
Physical insights on negative capacitance transistors in nonhysteresis and hysteresis regimes: MFMIS versus MFIS structures
G Pahwa, T Dutta, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 65 (3), 867-873, 2018
1012018
Analytical modeling of the suspended-gate FET and design insights for low-power logic
K Akarvardar, C Eggimann, D Tsamados, YS Chauhan, GC Wan, ...
IEEE transactions on Electron Devices 55 (1), 48-59, 2007
1002007
BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control
S Khandelwal, YS Chauhan, DD Lu, S Venugopalan, MAU Karim, ...
IEEE Transactions on Electron Devices 59 (8), 2019-2026, 2012
992012
Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Subthreshold behavior
G Pahwa, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 65 (11), 5130-5136, 2018
952018
Compact model for ferroelectric negative capacitance transistor with MFIS structure
G Pahwa, T Dutta, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 64 (3), 1366-1374, 2017
842017
Capacitance modeling in dual field-plate power GaN HEMT for accurate switching behavior
SA Ahsan, S Ghosh, K Sharma, A Dasgupta, S Khandelwal, YS Chauhan
IEEE Transactions on Electron Devices 63 (2), 565-572, 2015
792015
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM
T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan
IEEE Electron Device Letters 38 (8), 1161-1164, 2017
782017
BSIM—Industry standard compact MOSFET models
YS Chauhan, S Venugopalan, MA Karim, S Khandelwal, N Paydavosi, ...
2012 Proceedings of the European Solid-State Device Research Conference …, 2012
772012
RF SOI switch FET design and modeling tradeoffs for GSM applications
S Parthasarathy, A Trivedi, S Sirohi, R Groves, M Olsen, YS Chauhan, ...
2010 23rd International Conference on VLSI Design, 194-199, 2010
732010
ASM GaN: Industry standard model for GaN RF and power devices—Part 1: DC, CV, and RF model
S Khandelwal, YS Chauhan, TA Fjeldly, S Ghosh, A Pampori, D Mahajan, ...
IEEE Transactions on Electron Devices 66 (1), 80-86, 2018
712018
Thickness and electric-field-dependent polarizability and dielectric constant in phosphorene
P Kumar, BS Bhadoria, S Kumar, S Bhowmick, YS Chauhan, A Agarwal
Physical Review B 93 (19), 195428, 2016
662016
Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance
H Amrouch, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan
IEEE Access 6, 52754-52765, 2018
652018
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X IONusing compact modeling approach
G Pahwa, T Dutta, A Agarwal, YS Chauhan
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 49-54, 2016
632016
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