Jean-Luc Beuchat
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High-speed software implementation of the optimal ate pairing over Barreto–Naehrig curves
JL Beuchat, J González-Díaz, S Mitsunari, E Okamoto, ...
Pairing-Based Cryptography-Pairing 2010, 21-39, 2010
Static and dynamic configurable systems
E Sanchez, M Sipper, JO Haenni, JL Beuchat, A Stauffer, A Perez-Uribe
Computers, IEEE Transactions on 48 (6), 556-564, 1999
An algorithm for the nt pairing calculation in characteristic three and its hardware implementation
JL Beuchat, M Shirase, T Takagi, E Okamoto
18th IEEE Symposium on Computer Arithmetic (ARITH'07), 97-104, 2007
Algorithms and arithmetic operators for computing the ηT pairing in characteristic three
JL Beuchat, N Brisebarre, J Detrey, E Okamoto, M Shirase, T Takagi
IEEE Transactions on Computers 57 (11), 1454-1468, 2008
Multi-core implementation of the Tate pairing over supersingular elliptic curves
JL Beuchat, E López-Trejo, L Martínez-Ramos, S Mitsunari, ...
Cryptology and Network Security, 413-432, 2009
A Comparison between Hardware Accelerators for the Modified Tate Pairing over\ mathbbF 2 m F _ 2^ m and\ mathbbF 3 m F _ 3^ m
JL Beuchat, N Brisebarre, J Detrey, E Okamoto, F Rodríguez-Henríquez
Pairing-Based Cryptography–Pairing 2008, 297-315, 2008
Some modular adders and multipliers for field programmable gate arrays
JL Beuchat
Proceedings International Parallel and Distributed Processing Symposium, 8 pp., 2003
Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA
JL Beuchat, E Okamoto, T Yamazaki
Field-Programmable Technology (FPT), 2010 International Conference on, 170-177, 2010
Arithmetic operators for pairing-based cryptography
JL Beuchat, N Brisebarre, J Detrey, E Okamoto
Cryptographic Hardware and Embedded Systems-CHES 2007, 239-255, 2007
Fast Architectures for the\eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves
JL Beuchat, J Detrey, N Estibals, E Okamoto, F Rodríguez-Henríquez
IEEE Transactions on Computers 60 (2), 266-281, 2010
Automatic generation of modular multipliers for FPGA applications
JL Beuchat, JM Muller
IEEE Transactions on Computers 57 (12), 1600-1613, 2008
Von Neumann's 29-state cellular automaton: a hardware implementation
JL Beuchat, JO Haenni
IEEE Transactions on Education 43 (3), 300-308, 2000
Compact hardware implementations of chacha, blake, threefish, and skein on fpga
N At, JL Beuchat, E Okamoto, I San, T Yamazaki
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (2), 485-498, 2013
Optimal Eta pairing on supersingular genus-2 binary hyperelliptic curves
D Aranha, JL Beuchat, J Detrey, N Estibals
Topics in Cryptology–CT-RSA 2012, 98-115, 2012
FPGA and ASIC implementations of the ηT pairing in characteristic three
JL Beuchat, H Doi, K Fujita, A Inomata, P Ith, A Kanaoka, M Katouno, ...
Computers & electrical engineering 36 (1), 73-87, 2010
Modulo M multiplication-addition: algorithms and FPGA implementation
JL Beuchat, JM Muller
Electronics Letters 40 (11), 654-655, 2004
FPGA implementation of a recently published signature scheme
JL Beuchat, N Sendrier, A Tisserand, G Villard
INRIA, LIP, 2004
Modular multiplication for FPGA implementation of the IDEA block cipher
JL Beuchat
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
Hardware reconfigurable neural networks
JL Beuchat, JO Haenni, E Sanchez
Parallel and Distributed Processing, 91-98, 1998
Small multiplier-based multiplication and division operators for Virtex-II devices
JL Beuchat, A Tisserand
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002
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