A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS A Mishra, AJ Raymond, LG Amaru, G Sarkis, C Leroux, P Meinerzhagen, ...
2012 IEEE Asian solid state circuits conference (A-SSCC), 205-208, 2012
112 2012 Benchmarking of Standard-Cell Based Memories in the Sub- P Meinerzhagen, SMY Sherazi, A Burg, JN Rodrigues
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (2 …, 2011
98 2011 A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11 n in 90 nm CMOS C Roth, P Meinerzhagen, C Studer, A Burg
2010 IEEE Asian Solid-State Circuits Conference, 1-4, 2010
93 2010 Towards generic low-power area-efficient standard cell based memory architectures P Meinerzhagen, C Roth, A Burg
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 129-132, 2010
90 2010 Power, area, and performance optimization of standard cell memory arrays through controlled placement A Teman, D Rossi, P Meinerzhagen, L Benini, A Burg
ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (4 …, 2016
77 2016 Energy/reliability trade-offs in low-voltage ReRAM-based non-volatile flip-flop design I Kazi, P Meinerzhagen, PE Gaillardon, D Sacchetto, Y Leblebici, A Burg, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (11), 3155-3164, 2014
77 2014 A low-voltage radiation-hardened 13T SRAM bitcell for ultralow power space applications L Atias, A Teman, R Giterman, P Meinerzhagen, A Fish
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …, 2016
57 2016 Single-supply 3T gain-cell for low-voltage low-power applications R Giterman, A Teman, P Meinerzhagen, L Atias, A Burg, A Fish
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 358-362, 2015
54 2015 Exploration of Sub-V T and Near-V T 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling P Meinerzhagen, A Teman, R Giterman, A Burg, A Fish
Journal of Low Power Electronics and Applications 3 (2), 54-72, 2013
52 2013 TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing J Constantin, A Dogan, O Andersson, P Meinerzhagen, JN Rodrigues, ...
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012
47 2012 Gain-cell Embedded DRAMs for Low-power VLSI Systems-on-chip P Meinerzhagen, A Teman, R Giterman, N Edri, A Burg, A Fish
Springer International Publishing, 2018
46 2018 Review and classification of gain cell eDRAM implementations A Teman, P Meinerzhagen, A Burg, A Fish
2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 1-5, 2012
45 2012 A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS P Meinerzhagen, O Andersson, B Mohammadi, Y Sherazi, A Burg, ...
2012 Proceedings of the ESSCIRC (ESSCIRC), 321-324, 2012
41 2012 Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI A Teman, D Rossi, P Meinerzhagen, L Benini, A Burg
The 20th Asia and South Pacific Design Automation Conference, 81-86, 2015
38 2015 Replica technique for adaptive refresh timing of gain-cell-embedded DRAM A Teman, P Meinerzhagen, R Giterman, A Fish, A Burg
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (4), 259-263, 2014
37 2014 A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write I Kazi, P Meinerzhagen, PE Gaillardon, D Sacchetto, A Burg, G De Micheli
2013 IEEE 11th international new circuits and systems conference (NEWCAS), 1-4, 2013
35 2013 An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS P Meinerzhagen, C Tokunaga, A Malavasi, V Vaidya, A Mendon, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 38-40, 2018
32 2018 Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories A Teman, G Karakonstantis, R Giterman, P Meinerzhagen, A Burg
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 489-494, 2015
32 2015 Ultra low voltage synthesizable memories: A trade-off discussion in 65 nm CMOS O Andersson, B Mohammadi, P Meinerzhagen, A Burg, JN Rodrigues
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (6), 806-817, 2016
29 2016 4T gain-cell with internal-feedback for ultra-low retention power at scaled CMOS nodes R Giterman, A Teman, P Meinerzhagen, A Burg, A Fish
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2177-2180, 2014
29 2014 
Andreas BurgEPFL - Telecommunications Circuits LaboratoryAdresse e-mail validée de epfl.ch
