Arunachalam Annamalai
Arunachalam Annamalai
CPU Performance Modeling and Analysis at AMD
Verified email at ecs.umass.edu
Title
Cited by
Cited by
Year
A study on the use of performance counters to estimate power in microprocessors
R Rodrigues, A Annamalai, I Koren, S Kundu
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (12), 882-886, 2013
572013
Performance per watt benefits of dynamic core morphing in asymmetric multicores
R Rodrigues, A Annamalai, I Koren, S Kundu, O Khan
2011 International Conference on Parallel Architectures and Compilation …, 2011
482011
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs
A Annamalai, R Rodrigues, I Koren, S Kundu
Proceedings of the 22nd international conference on Parallel architectures …, 2013
362013
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing
R Rodrigues, A Annamalai, I Koren, S Kundu
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (1 …, 2013
212013
Scalable thread scheduling in asymmetric multicores for power efficiency
R Rodrigues, A Annamalai, I Koren, S Kundu
2012 IEEE 24th international symposium on computer architecture and high …, 2012
202012
Dynamic thread scheduling in asymmetric multicores to maximize performance-per-watt
A Annamalai, R Rodrigues, I Koren, S Kundu
2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012
172012
Reducing energy per instruction via dynamic resource allocation and voltage and frequency adaptation in asymmetric multicores
A Annamalai, R Rodrigues, I Koren, S Kundu
2014 IEEE Computer Society Annual Symposium on VLSI, 436-441, 2014
72014
A study on polymorphing superscalar processor dynamically to improve power efficiency
S Srinivasan, R Rodrigues, A Annamalai, I Koren, S Kundu
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 46-51, 2013
42013
A system-level solution for managing spatial temperature gradients in thinned 3D ICs
A Annamalai, R Kumar, A Vijayakumar, S Kundu
International Symposium on Quality Electronic Design (ISQED), 88-95, 2013
42013
A low-power instruction replay mechanism for design of resilient microprocessors
R Rodrigues, A Annamalai, S Kundu
ACM Transactions on Embedded Computing Systems (TECS) 13 (4), 1-23, 2014
22014
A dynamic reconfiguration framework to maximize performance/power in asymmetric multicore processors
A Annamalai
12013
Using loop exit prediction to accelerate or suppress loop mode of a processor
A Annamalai, M Evers, A Thyagarajan
US Patent App. 16/134,440, 2020
2020
Branch target buffer with early return prediction
A Thyagarajan, M Evers, A Annamalai
US Patent App. 16/043,293, 2020
2020
Low latency synchronization for operation cache and instruction cache fetching and decoding instructions
M Evers, DB Tavare, AT Venkatachar, A Annamalai, DA Priore, ...
US Patent App. 16/014,715, 2019
2019
On dynamic polymorphing of a superscalar core for improving energy efficiency
S Srinivasan, R Rodrigues, A Annamalai, I Koren, S Kundu
2013 IEEE 31st International Conference on Computer Design (ICCD), 495-498, 2013
2013
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