Jia Di
Jia Di
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Designing asynchronous circuits using NULL convention logic (NCL)
S Smith, J Di
Springer Nature, 2022
Reversible-logic design with online testability
DP Vasudevan, PK Lala, J Di, JP Parkerson
IEEE transactions on instrumentation and measurement 55 (2), 406-414, 2006
High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders
J Di, JS Yuan, R DeMara
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 260-261, 2003
Fingerprinting RFID tags
SCG Periaswamy, DR Thompson, J Di
IEEE Transactions on Dependable and Secure Computing 8 (6), 938-943, 2010
An overview of cyber-physical security of battery management systems and adoption of blockchain technology
T Kim, J Ochoa, T Faika, HA Mantooth, J Di, Q Li, Y Lee
IEEE Journal of Emerging and Selected Topics in Power Electronics 10 (1 …, 2020
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design
J Di, JS Yuan, R Demara
Integration 39 (2), 90-112, 2006
Multi-threshold asynchronous circuit design for ultra-low power
A Bailey, A Al Zahrani, G Fu, J Di, S Smith
Journal of Low Power Electronics 4 (3), 337-348, 2008
Multi-Threshold NULL Convention Logic (MTNCL): An ultra-low power asynchronous circuit design methodology
L Zhou, R Parameswaran, FA Parsan, SC Smith, J Di
Journal of low power electronics and applications 5 (2), 81-100, 2015
Complex high-temperature CMOS silicon carbide digital circuit designs
N Kuhns, L Caley, A Rahman, S Ahmed, J Di, HA Mantooth, AM Francis, ...
IEEE Transactions on Device and Materials Reliability 16 (2), 105-111, 2016
Fork path: improving efficiency of oram by removing redundant memory accesses
X Zhang, G Sun, C Zhang, W Zhang, Y Liang, T Wang, Y Chen, J Di
Proceedings of the 48th International Symposium on Microarchitecture, 102-114, 2015
The inhibition of hepatic bile acids transporters Ntcp and Bsep is involved in the pathogenesis of isoniazid/rifampicin-induced hepatotoxicity
YX Guo, XF Xu, QZ Zhang, C Li, Y Deng, P Jiang, LY He, WX Peng
Toxicology mechanisms and methods 25 (5), 382-387, 2015
Chip-level anti-reverse engineering using transformable interconnects
S Chen, J Chen, D Forte, J Di, M Tehranipoor, L Wang
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015
High-temperature SiC CMOS comparator and op-amp for protection circuits in voltage regulators and switch-mode converters
A Rahman, S Roy, R Murphree, R Kotecha, K Addington, A Abbasi, ...
IEEE Journal of Emerging and Selected Topics in Power Electronics 4 (3), 935-945, 2016
Ultra-low power delay-insensitive circuit design
AD Bailey, J Di, SC Smith, HA Mantooth
2008 51st Midwest Symposium on Circuits and Systems, 503-506, 2008
Delay-insensitive asynchronous ALU for cryogenic temperature environments
B Hollosi, M Barlow, G Fu, C Lee, J Di, SC Smith, HA Mantooth, ...
2008 51st Midwest Symposium on Circuits and Systems, 322-325, 2008
Mitigating power-and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic
W Cilio, M Linder, C Porter, J Di, DR Thompson, SC Smith
Microelectronics Journal 44 (3), 258-269, 2013
Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology
L Zhou, SC Smith, J Di
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 217-220, 2010
A family of CMOS analog and mixed signal circuits in SiC for high temperature electronics
A Rahman, PD Shepherd, SA Bhuyan, S Ahmed, SK Akula, L Caley, ...
2015 IEEE Aerospace Conference, 1-10, 2015
Ultra-low power multi-threshold asynchronous circuit design
J Di, SC Smith
US Patent 7,977,972, 2011
A hardware threat modeling concept for trustable integrated circuits
J Di, S Smith
2007 IEEE Region 5 Technical Conference, 354-357, 2007
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