| A VLSI architecture and algorithm for Lucas–Kanade-based optical flow computation V Mahalingam, K Bhattacharya, N Ranganathan, H Chakravarthula, ... IEEE transactions on very large scale integration (VLSI) systems 18 (1), 29-38, 2009 | 63 | 2009 |
| Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems C Verrilli, C Waldspurger, N Vaidhyanathan, M Heddes, K Bhattacharya US Patent 10,055,158, 2018 | 61 | 2018 |
| Redundancy mining for soft error detection in multicore processors R Hyman, K Bhattacharya, N Ranganathan IEEE Transactions on Computers 60 (8), 1114-1125, 2010 | 36 | 2010 |
| Providing efficient multiplication of sparse matrices in matrix-processor-based devices MCAA Heddes, R Dreyer, CB Verrilli, N Vaidhyanathan, K Bhattacharya US Patent 10,725,740, 2020 | 31 | 2020 |
| A linear programming formulation for security-aware gate sizing K Bhattacharya, N Ranganathan Proceedings of the 18th ACM Great Lakes symposium on VLSI, 273-278, 2008 | 28 | 2008 |
| A framework for correction of multi-bit soft errors in L2 caches based on redundancy K Bhattacharya, N Ranganathan, S Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (2), 194-206, 2008 | 25 | 2008 |
| Multiple exemplar-based facial image retrieval using independent component analysis J Basak, K Bhattacharya, S Chaudhury IEEE Transactions on Image Processing 15 (12), 3773-3783, 2006 | 22 | 2006 |
| RADJAM: A novel approach for reduction of soft errors in logic circuits K Bhattacharya, N Ranganathan 2009 22nd International Conference on VLSI Design, 453-458, 2009 | 19 | 2009 |
| Providing matrix multiplication using vector registers in processor-based devices R Dreyer, MCAA Heddes, CB Verrilli, N Vaidhyanathan, K Bhattacharya US Patent App. 16/129,480, 2019 | 16 | 2019 |
| Improving the reliability of on-chip l2 cache using redundancy K Bhattacharya, S Kim, N Ranganathan 2007 25th International Conference on Computer Design, 224-229, 2007 | 11 | 2007 |
| Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power K Bhattacharya, N Ranganathan Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | 10 | 2008 |
| A strategy for soft error reduction in multi core designs R Hyman, K Bhattacharya, N Ranganathan 2009 IEEE International Symposium on Circuits and Systems, 2217-2220, 2009 | 9 | 2009 |
| A new placement algorithm for reduction of soft errors in macrocell based design of nanometer circuits K Bhattacharya, N Ranganathan 2009 IEEE Computer Society Annual Symposium on VLSI, 91-96, 2009 | 9 | 2009 |
| Methodology and apparatus for reduction of soft errors in logic circuits N Ranganathan, K Bhattacharya US Patent 7,944,230, 2011 | 8 | 2011 |
| Placement for immunity of transient faults in cell-based design of nanometer circuits K Bhattacharya, N Ranganathan IEEE transactions on very large scale integration (VLSI) systems 19 (5), 918-923, 2010 | 5 | 2010 |
| Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices CB Verrilli, MCAA Heddes, N Vaidhyanathan, K Bhattacharya, R Dreyer US Patent 10,936,943, 2021 | 4 | 2021 |
| Providing efficient floating-point operations using matrix processors in processor-based systems MCAA Heddes, N Vaidhyanathan, R Dreyer, CB Verrilli, K Bhattacharya US Patent 10,747,501, 2020 | 4 | 2020 |
| A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations K Bhattacharya, N Ranganathan 2009 10th International Symposium on Quality Electronic Design, 388-393, 2009 | 4 | 2009 |
| Architectures and Algorithms for Mitigation of Soft Errors in Nanoscale VLSI Circuits K Bhattacharya | 3 | 2009 |
| Video Summarization: A Machine Learning Based Approach. K Bhattacharya, S Chaudhury, J Basak ICVGIP, 429-434, 2004 | 3 | 2004 |
Nagarajan RanganathanDistinguished University Professor Emeritus of Computer Science, University of South FloridaVerified email at cse.usf.edu
