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Rolf Ernst
Rolf Ernst
Professor at Institute of Computer and Network Engineering, TU Braunschweig, Germany
Bestätigte E-Mail-Adresse bei tu-bs.de - Startseite
Titel
Zitiert von
Zitiert von
Jahr
Hardware-software cosynthesis for microcontrollers
R Ernst, J Henkel, T Benner
IEEE Design & Test of computers 10 (4), 64-75, 1993
9941993
Hardware/software co-design
G De Michell, RK Gupta
Proceedings of the IEEE 85 (3), 349-365, 1997
888*1997
System level performance analysis–the SymTA/S approach
R Henia, A Hamann, M Jersak, R Racu, K Richter, R Ernst
IEE Proceedings-Computers and Digital Techniques 152 (2), 148-166, 2005
6702005
Readings in hardware/software co-design
G De Micheli, R Ernst, W Wolf
Morgan Kaufmann, 2002
2772002
Codesign of embedded systems: Status and trends
R Ernst
IEEE Design & Test of Computers 15 (2), 45-54, 1998
2751998
A formal approach to MpSoC performance verification
K Richter, M Jersak, R Ernst
Computer 36 (4), 60-67, 2003
2002003
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques
J Henkel, R Ernst
IEEE transactions on very large scale integration (VLSI) systems 9 (2), 273-289, 2001
1882001
Embedded program timing analysis based on path clustering and architecture classification
Ernst
1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997
1701997
Building timing predictable embedded systems
P Axer, R Ernst, H Falk, A Girault, D Grund, N Guan, B Jonsson, ...
ACM Transactions on Embedded Computing Systems (TECS) 13 (4), 1-37, 2014
1632014
Scheduling analysis of real-time systems with precise modeling of cache related preemption delay
J Staschulat, S Schliecker, R Ernst
17th Euromicro Conference on Real-Time Systems (ECRTS'05), 41-48, 2005
1602005
Mixed criticality systems—a history of misconceptions?
R Ernst, M Di Natale
IEEE Design & Test 33 (5), 65-74, 2016
1532016
Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching
J Diemer, D Thiele, R Ernst
7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), 1-10, 2012
1352012
Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers
D Thiele, R Ernst, J Diemer
2015 IEEE Vehicular Networking Conference (VNC), 251-258, 2015
1222015
Hardware-software codesign of embedded controllers based on hardware extraction
R Ernst
The First International Workshop on Hardware-Software Codesign, 1992
1211992
Design and architectures for dependable embedded systems
J Henkel, L Bauer, J Becker, O Bringmann, U Brinkschulte, S Chakraborty, ...
Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011
1202011
Event model interfaces for heterogeneous system analysis
K Richter, R Ernst
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
1162002
A hardware/software partitioner using a dynamically determined granularity
J Henkel, R Ernst
Proceedings of the 34th annual Design Automation Conference, 691-696, 1997
1161997
Bounding the shared resource load for the performance analysis of multiprocessor systems
S Schliecker, M Negrean, R Ernst
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
1042010
Formal worst-case performance analysis of time-sensitive ethernet with frame preemption
D Thiele, R Ernst
2016 IEEE 21st International Conference on Emerging Technologies and Factory …, 2016
1032016
The shift to multicores in real-time and safety-critical systems
S Saidi, R Ernst, S Uhrig, H Theiling, BD de Dinechin
2015 International Conference on Hardware/Software Codesign and System …, 2015
1032015
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