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Manu Perumkunnil Komalan
Manu Perumkunnil Komalan
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Cited by
Year
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
S Sakhare, M Perumkunnil, TH Bao, S Rao, W Kim, D Crotti, F Yasin, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.3.1-18.3.4, 2019
702019
Voltage-gate-assisted spin-orbit-torque magnetic random-access memory for high-density and low-power embedded applications
YC Wu, K Garello, W Kim, M Gupta, M Perumkunnil, V Kateel, S Couet, ...
Physical Review Applied 15 (6), 064015, 2021
642021
Spin-orbit torque switching of magnetic tunnel junctions for memory applications
V Krizakova, M Perumkunnil, S Couet, P Gambardella, K Garello
Journal of Magnetism and Magnetic Materials 562, 169692, 2022
472022
High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node
M Gupta, M Perumkunnil, K Garello, S Rao, F Yasin, GS Kar, A Furnémont
2020 IEEE international electron devices meeting (IEDM), 24.5. 1-24.5. 4, 2020
392020
System level exploration of a STT-MRAM based level 1 data-cache
MP Komalan, C Tenllado, JIG Pérez, FT Fernández, F Catthoor
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
252015
Heterogeneous 3D integration for a RISC-V system with STT-MRAM
L Zhu, L Bamberg, A Agnesina, F Catthoor, D Milojevic, M Komalan, ...
IEEE Computer Architecture Letters 19 (1), 51-54, 2020
192020
IGZO-based compute cell for analog in-memory computing—DTCO analysis to enable ultralow-power AI at edge
D Saito, J Doevenspeck, S Cosemans, H Oh, M Perumkunnil, IA Papistas, ...
IEEE Transactions on Electron Devices 67 (11), 4616-4620, 2020
182020
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems
M Komalan, S Sakhare, TH Bao, S Rao, W Kim, C Tenllado, JI Gómez, ...
Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, 1-4, 2017
172017
Buried power SRAM DTCO and system-level benchmarking in N3
S Salahuddin, M Perumkunnil, ED Litta, A Gupta, P Weckx, J Ryckaert, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
152020
Feasibility exploration of NVM based I-cache through MSHR enhancements
M Komalan, JIG Pérez, C Tenllado, P Raghavan, M Hartmann, F Catthoor
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
152014
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application
S Rao, W Kim, S Van Beek, S Kundu, M Perumkunnil, S Cosemans, ...
2021 IEEE International Memory Workshop (IMW), 1-4, 2021
142021
Cim-based robust logic accelerator using 28 nm stt-mram characterization chip tape-out
A Singh, M Zahedi, T Shahroodi, M Gupta, A Gebregiorgis, M Komalan, ...
2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022
132022
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
M Komalan, OH Rock, M Hartmann, S Sakhare, C Tenllado, JI Gómez, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 103-108, 2018
122018
Atomic insight into Ge1− xSnx using atom probe tomography
A Kumar, MP Komalan, H Lenka, AK Kambham, M Gilbert, F Gencarelli, ...
Ultramicroscopy 132, 171-178, 2013
122013
A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs
T Evenblij, M Perumkunnil, F Catthoor, S Sakhare, P Debacker, G Kar, ...
2019 IEEE 37th International Conference on Computer Design (ICCD), 255-263, 2019
112019
JSWof 5.5 MA/cm2 and RA of 5.2-Ω · μm2 STT-MRAM Technology for LLC Application
S Sakhare, S Rao, M Perumkunnil, S Couet, D Crotti, S Van Beek, ...
IEEE Transactions on Electron Devices 67 (9), 3618-3625, 2020
92020
System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs
M Perumkunnil, F Yasin, S Rao, SM Salahuddin, D Milojevic, ...
2020 IEEE International Electron Devices Meeting (IEDM), 15.4. 1-15.4. 4, 2020
82020
Non-volatile SRAM cell using resistive memory elements
S Sakhare, TH Bao, MK Perumkunnil
US Patent 10,325,647, 2019
82019
High-performance logic-on-memory monolithic 3-D IC designs for arm Cortex-A processors
L Zhu, L Bamberg, SSK Pentapati, K Chang, F Catthoor, D Milojevic, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (6 …, 2021
72021
Workload-aware electromigration analysis in emerging spintronic memory arrays
SM Nair, M Mayahinia, MB Tahoori, M Perumkunnil, H Zahedmanesh, ...
IEEE Transactions on Device and Materials Reliability 21 (2), 258-266, 2021
72021
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