| Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture B Gaide, D Gaitonde, C Ravishankar, T Bauer Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 93 | 2019 |
| FPGA power reduction by guarded evaluation JH Anderson, C Ravishankar Proceedings of the 18th annual ACM/SIGDA international symposium on Field …, 2010 | 14 | 2010 |
| Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms C Ravishankar, S Ananthanarayanan, S Garg, A Kennings Thirteenth International Symposium on Quality Electronic Design (ISQED), 617-624, 2012 | 12 | 2012 |
| FPGA power reduction by guarded evaluation considering logic architecture C Ravishankar, JH Anderson, A Kennings IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 11 | 2012 |
| Raising FPGA logic density through synthesis-inspired architecture JH Anderson, Q Wang, C Ravishankar IEEE transactions on very large scale integration (VLSI) systems 20 (3), 537-550, 2011 | 11 | 2011 |
| Placement strategies for 2.5 D FPGA fabric architectures C Ravishankar, D Gaitonde, T Bauer 2018 28th International Conference on Field Programmable Logic and …, 2018 | 8 | 2018 |
| EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip C Ravishankar, S Ananthanarayan, S Garg, A Kennings 22nd International Conference on Field Programmable Logic and Applications …, 2012 | 6 | 2012 |
| Parallel FPGA technology mapping using multi-core architectures A Kennings, C Ravishankar 2011 24th Canadian Conference on Electrical and Computer Engineering (CCECE …, 2011 | 4 | 2011 |
| Method and system for making pin-to-pin signal connections C Ravishankar, D Moore US Patent 10,810,341, 2020 | 2 | 2020 |
| EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip S Ananthanarayanan, C Ravishankar, S Garg, A Kennings Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 2 | 2012 |
| SAT based Place-And-Route for High-Speed Designs on 2.5 D FPGAs C Ravishankar, H Fraisse, D Gaitonde 2018 International Conference on Field-Programmable Technology (FPT), 118-125, 2018 | 1 | 2018 |
| Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing S Shrivastava, S Nikolic, C Ravishankar, D Gaitonde, M Stojilovic Proceedings of the 2023 ACM/SIGDA International Symposium on Field …, 2023 | | 2023 |
| Resolving timing violations in multi-die circuit designs H Fraisse, DD Gaitonde, C Ravishankar US Patent 10,747,929, 2020 | | 2020 |
| Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements EF Dellinger, JT Young, BC Gaide, C Ravishankar, D Moore, SP Young US Patent 10,715,149, 2020 | | 2020 |
| FPGA power reduction by guarded evaluation considering physical information C Ravishankar, A Kennings, J Anderson 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012 | | 2012 |
| Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs C Ravishankar University of Waterloo, 2012 | | 2012 |
| Parallel FPGA Technology Mapping Using Multi-core Processors AA Kennings, C Ravishankar Department of Electrical and Computer Engineering, University of Waterloo, 2010 | | 2010 |
| Technical program A Le Masle, W Luk, S Mane, M Taha, P Schaumont, G Eichinger, ... | | |
| FPL 2018 H Fraisse, D Gaitonde, C Ravishankar, T Bauer | | |
Jason AndersonProfessor of Electrical and Computer Engineering, University of TorontoVerified email at eecg.toronto.edu
