| Formal verification of integer multipliers by combining Gröbner basis with logic reduction A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016 …, 2016 | 99 | 2016 |
| Equivalence checking using Gröbner bases A Sayed-Ahmed, D Große, M Soeken, R Drechsler 2016 Formal Methods in Computer-Aided Design (FMCAD), 169-176, 2016 | 31 | 2016 |
| Three engines to solve verification constraints of decimal floating-point operation AAR Sayed-Ahmed, HAH Fahmy, MY Hassan 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals …, 2010 | 17 | 2010 |
| Verification of the decimal floating-point square root operation AS Ahmed, H Fahmy, U Kühne 2014 19th IEEE European Test Symposium (ETS), 1-2, 2014 | 6 | 2014 |
| SoCINT: Resilient system-on-chip via dynamic intrusion detection A Sayed-Ahmed, J Haj-Yahya, A Chattopadhyay 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 4 | 2019 |
| Verification of decimal floating-point fused-multiply-add operation AAR Sayed-Ahmed, HAH Fahmy, R Samy 2011 9th IEEE/ACS International Conference on Computer Systems and …, 2011 | 4 | 2011 |
| Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits A Sayed-Ahmed, U Kühne, D Große, R Drechsler IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, 1-6, 2015 | 3 | 2015 |
| Verification of Decimal Floating-Point Operations AA Sayed-Ahmed Master’s Thesis, 2011 | 1 | 2011 |
| Highly Automated Formal Verification of Arithmetic Circuits A Sayed-Ahmed Universität Bremen, 2017 | | 2017 |
Daniel GrosseFull Professor at Johannes Kepler University LinzVerified email at jku.at
