| Efficient sensing approaches for high-density memristor sensor array A Adeyemo, J Mathew, A Jabir, CD Natale, E Martinelli, M Ottavi Journal of Computational Electronics 17, 1285-1296, 2018 | 27 | 2018 |
| Novel techniques for memristive multifunction logic design X Yang, A Adeyemo, A Bala, A Jabir Integration 65, 219-230, 2019 | 15 | 2019 |
| High-performance single-cycle memristive multifunction logic architecture X Yang, AA Adeyemo, A Jabir, J Mathew Electronics Letters 52 (11), 906-907, 2016 | 12 | 2016 |
| Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme A Adeyemo, A Jabir, J Mathew Journal of Low Power Electronics 13 (4), 649-660, 2017 | 11 | 2017 |
| Novel memristive logic architectures X Yang, A Adeyemo, A Bala, A Jabir 2016 26th International Workshop on Power and Timing Modeling, Optimization …, 2016 | 11 | 2016 |
| Reliable gas sensing with memristive array A Adeyemo, A Jabir, J Mathew, E Martinelli, C Di Natale, M Ottavi 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System …, 2017 | 9 | 2017 |
| Learning method for ex-situ training of memristor crossbar based multi-layer neural network A Bala, A Adeyemo, X Yang, A Jabir 2017 9th International Congress on Ultra Modern Telecommunications and …, 2017 | 6 | 2017 |
| Analytic models for crossbar write operation A Adeyemo, X Yang, A Bala, A Jabir 2016 Sixth International Symposium on Embedded Computing and System Design …, 2016 | 6 | 2016 |
| Parasitic effects on memristive logic architecture X Yang, A Adeyemo, A Bala, A Jabir 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 5 | 2017 |
| High level abstraction of memristor model for neural network simulation A Bala, A Adeyemo, X Yang, A Jabir 2016 Sixth International Symposium on Embedded Computing and System Design …, 2016 | 5 | 2016 |
| Write scheme for multiple Complementary Resistive Switch (CRS) cells A Adeyemo, J Mathew, A Jabir, D Pradhan 2014 24th International Workshop on Power and Timing Modeling, Optimization …, 2014 | 5 | 2014 |
| A Memristive Activation Circuit for Deep Learning Neural Networks A Bala, X Yang, A Adeyemo, A Jabir 2018 8th International Symposium on Embedded Computing and System Design …, 2018 | 4 | 2018 |
| Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays AA Adeyemo, J Mathew, AM Jabir, DK Pradhan 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015 | 4 | 2015 |
| Analytic models for crossbar read operation A Adeyemo, X Yang, A Bala, J Mathew, A Jabir 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016 | 2 | 2016 |
| Memristor based sensor A Jabir, M Ottavi, J Mathew, E Martinelli, C Di Natale, A Adeyemo US Patent 10,996,182, 2021 | | 2021 |
| Memristor based logic gate AM Jabir, X Yang, AA Adeyemo US Patent 10,860,291, 2020 | | 2020 |
| MEMRISTOR BASED SENSOR A Jabir, M Ottavi, J Mathew, E Martinelli, C Di Natale, A Adeyemo | | 2019 |
| Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks A Bala, X Yang, A Adeyemo, A Jabir Journal of Low Power Electronics 15 (2), 214-223, 2019 | | 2019 |
| Design and analysis of memristor-based reliable crossbar architectures AA Adeyemo Oxford Brookes University, 2018 | | 2018 |
| Research Archive and Digital Asset Repository X Yang, A Adeyemo, A Jabir, J Matthew | | |
