Follow
Odysseas Zografos
Odysseas Zografos
R&D team leader, imec, Leuven, Belgium
Verified email at imec.be - Homepage
Title
Cited by
Cited by
Year
Enabling sub-5nm CMOS technology scaling thinner and taller!
J Ryckaert, MH Na, P Weckx, D Jang, P Schuddinck, B Chehab, S Patli, ...
2019 IEEE International Electron Devices Meeting (IEDM), 29.4. 1-29.4. 4, 2019
672019
Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm
D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ...
2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019
642019
Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS
O Zografos, B Sorée, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ...
2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015
612015
Device-, circuit-& block-level evaluation of CFET in a 4 track library
P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ...
2019 Symposium on VLSI Technology, T204-T205, 2019
422019
Non-volatile spin wave majority gate at the nanoscale
O Zografos, S Dutta, M Manfrini, A Vaysset, B Sorée, A Naeemi, ...
Aip Advances 7 (5), 2017
362017
Spintronic majority gates
IP Radu, O Zografos, A Vaysset, F Ciubotaru, J Yan, J Swerts, D Radisic, ...
2015 IEEE International Electron Devices Meeting (IEDM), 32.5. 1-32.5. 4, 2015
342015
Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet
SMY Sherazi, M Cupak, P Weckx, O Zografos, D Jang, P Debacker, ...
Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019
322019
Inversion optimization in majority-inverter graphs
E Testa, M Soeken, O Zografos, L Amaru, P Raghavan, R Lauwereins, ...
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
292016
Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation
S Dutta, O Zografos, S Gurunarayanan, I Radu, B Soree, F Catthoor, ...
Scientific reports 7 (1), 17866, 2017
262017
Inverter propagation and fan-out constraints for beyond-CMOS majority-based technologies
E Testa, O Zografos, M Soeken, A Vaysset, M Manfrini, R Lauwereins, ...
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 164-169, 2017
222017
Chain of magnetic tunnel junctions as a spintronic memristor
E Raymenants, A Vaysset, D Wan, M Manfrini, O Zografos, O Bultynck, ...
Journal of Applied Physics 124 (15), 2018
212018
Exchange-driven magnetic logic
O Zografos, M Manfrini, A Vaysset, B Sorée, F Ciubotaru, C Adelmann, ...
Scientific reports 7 (1), 12154, 2017
212017
Wave pipelining for majority-based beyond-CMOS technologies
O Zografos, A De Meester, E Testa, M Soeken, PE Gaillardon, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
202017
Confined magnetoelastic waves in thin waveguides
F Vanderveken, J Mulkers, J Leliaert, B Van Waeyenberge, B Sorée, ...
Physical Review B 103 (5), 054439, 2021
182021
System-level assessment and area evaluation of spin wave logic circuits
O Zografos, P Raghavan, L Amaru, B Sorée, R Lauwereins, I Radu, ...
Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014
172014
Majority logic synthesis
L Amarù, E Testa, M Couceiro, O Zografos, G De Micheli, M Soeken
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2018
162018
Novel grid-based power routing scheme for regular controllable-polarity FET arrangements
O Zografos, PE Gaillardon, G De Micheli
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1416-1419, 2014
152014
First experimental demonstration of a scalable linear majority gate based on spin waves
F Ciubotaru, G Talmelli, T Devolder, O Zografos, M Heyns, C Adelmann, ...
2018 IEEE International Electron Devices Meeting (IEDM), 36.1. 1-36.1. 4, 2018
142018
Wide operating window spin-torque majority gate towards large-scale integration of logic circuits
A Vaysset, O Zografos, M Manfrini, D Mocuta, IP Radu
Aip Advances 8 (5), 2018
142018
Majority logic synthesis for spin wave technology
O Zografos, L Amaru, PE Gaillardon, P Raghavan, G De Micheli
2014 17th Euromicro Conference on Digital System Design, 691-694, 2014
132014
The system can't perform the operation now. Try again later.
Articles 1–20