| Neurostream: Scalable and energy efficient deep learning with smart memory cubes E Azarkhish, D Rossi, I Loi, L Benini IEEE Transactions on Parallel and Distributed Systems 29 (2), 420-434, 2017 | 134 | 2017 |
| Design and evaluation of a processing-in-memory architecture for the smart memory cube E Azarkhish, D Rossi, I Loi, L Benini Architecture of Computing Systems–ARCS 2016: 29th International Conference …, 2016 | 60 | 2016 |
| High performance AXI-4.0 based interconnect for extensible smart memory cubes E Azarkhish, D Rossi, I Loi, L Benini 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 43 | 2015 |
| Logic-base interconnect design for near memory computing in the smart memory cube E Azarkhish, C Pfister, D Rossi, I Loi, L Benini IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 210-223, 2016 | 34 | 2016 |
| A Logic-base interconnect for supporting near memory computation in the hybrid memory cube E Azarkhish, D Rossi, I Loi, L Benini Proceedings of the 2nd Workshop on Near-Data Processing, 2014 | 15 | 2014 |
| A case for three‐dimensional stacking of tightly coupled data memories over multi‐core clusters using low‐latency interconnects E Azarkhish, I Loi, L Benini IET computers & digital techniques 7 (5), 191-199, 2013 | 11 | 2013 |
| A sub-mW dual-engine ML inference system-on-chip for complete end-to-end face-analysis at the edge P Jokic, E Azarkhish, R Cattenoz, E Türetken, L Benini, S Emery 2021 Symposium on VLSI Circuits, 1-2, 2021 | 10 | 2021 |
| A case for near memory computation inside the smart memory cube E Azarkhish, D Rossi, I Loi, L Benini | 7 | 2016 |
| A construction kit for efficient low power neural network accelerator designs P Jokic, E Azarkhish, A Bonetti, M Pons, S Emery, L Benini ACM Transactions on Embedded Computing Systems (TECS) 21 (5), 1-36, 2022 | 5 | 2022 |
| A 20 channel EMG SoC with an integrated 32B RISC core for real-time wireless prosthetic control MP Sole, K Badami, J Deng, T Mavrogordatos, E Azarkhish, L Zahnd, ... ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), 73-76, 2019 | 5 | 2019 |
| A Modular Shared L2 Memory Design for 3-D Integration E Azarkhish, D Rossi, I Loi, L Benini Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2014 | 5 | 2014 |
| Single-battery cooperative sensors for multi-lead long term ambulatory ECG measurement K Badami, M Pons-Sole, E Azarkhish, A Fivaz, M Rapin, O Chételat, ... 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2021 | 4 | 2021 |
| A high-performance multiported L2 memory IP for scalable three-dimensional integration E Azarkhish, I Loi, L Benini 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-8, 2013 | 4 | 2013 |
| A hybrid instruction prefetching mechanism for ultra low-power multicore clusters M Payami, E Azarkhish, I Loi, L Benini IEEE Embedded Systems Letters 9 (4), 125-128, 2017 | 3 | 2017 |
| Memory hierarchy design for next generation scalable many-core platforms E Azarkhish alma, 2016 | 2 | 2016 |
| 3D logarithmic interconnect: stacking multiple L1 memory dies over multi-core clusters E Azarkhish, I Loi, L Benini 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 1-2, 2013 | 2 | 2013 |
| Benchmarking Neuromorphic Computing for Inference S Narduzzi, L Mateu, P Jokic, E Azarkhish, A Dunbar Industrial Artificial Intelligence Technologies and Applications, 1-19, 2023 | 1 | 2023 |
| 2018 Index IEEE Transactions on Parallel and Distributed Systems Vol. 29 TK Aasawat, P Abad, S Abadal, A Abdelfattah, TF Abdelzaher, S Abdulah, ... IEEE Transactions on Parallel and Distributed Systems 30 (1), 1, 2019 | | 2019 |
| 2015 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 23 SM Abbas, G Acconcia, A Afzali-Kusha, N Aghaee, A Aghaie, M Ahmadi, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12), 3153, 2015 | | 2015 |
| A statistical application model for fast MPSoC simulation E Azarkhish, O Fatemi 5th International Conference on Design & Technology of Integrated Systems in …, 2010 | | 2010 |
Luca BeniniETH Zürich, Università di BolognaAdresse e-mail validée de unibo.it
