Pillement Sébastien
Pillement Sébastien
Professeur des Universités, Université de Nantes
Verified email at univ-nantes.fr - Homepage
Title
Cited by
Cited by
Year
DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints
R David, D Chillet, S Pillement, O Sentieys
IEEE International Parallel and Distributed Processing Symposium, 2003
742003
FPGA side channel attacks without physical access
C Ramesh, SB Patil, SN Dhanuskodi, G Provelengios, S Pillement, ...
2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018
622018
Low Overhead Fault-Tolerance Technique for Dynamically Reconfigurable Softcore Processor
H Pham, S Pillement, S Piestrak
IEEE Transactions on Computers 99, 1-1, 2012
552012
DART: a Functional-Level Reconfigurable Architecture for High Energy Efficiency
S Pillement, O Sentieys, R David
EURASIP Journal on Embedded Systems, 5, 2008
432008
Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture: A Case Study
S Jafri, SJ Piestrak, O Sentieys, S Pillement
Quality Electronic Design (ISQED), 2010 11th International Symposium on, 845-852, 2010
41*2010
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures
F Lemonnier, P Millet, GM Almeida, M Hübner, J Becker, S Pillement, ...
Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2012
332012
UPaRC—Ultra-Fast Power-aware Reconfiguration Controller
R Bonamy, HM Pham, S Pillement, D Chillet
Design and Test in Europe, 2012
332012
Flexible interconnection network for dynamically and partially reconfigurable architectures
L Devaux, S Ben Sassi, S Pillement, D Chillet, D Demigny
International Journal of Reconfigurable Computing 2010, 2010
302010
Dart: A dynamically reconfigurable architecture dealing with next generation telecommunications constraints
R David, D Chillet, S Pillement, O Sentieys
9th IEEE Reconfigurable Architecture Workshop RAW, 2002
292002
Area efficient temporal coding schemes for reducing crosstalk effects
JM Philippe, S Pillement, O Sentieys
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-339, 2006
262006
Error recovery technique for coarse-grained reconfigurable architectures
MM Azeem, SJ Piestrak, O Sentieys, S Pillement
14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011
252011
A low-power and high-speed quaternary interconnection link using efficient converters
JM Philippe, S Pillement, O Sentieys
2005 IEEE International Symposium on Circuits and Systems, 4689-4692, 2005
242005
Designing efficient codecs for bus-invert berger code for fully asymmetric communication
SJ Piestrak, S Pillement, O Sentieys
iEEE transactions on circuits and systems ii: Express Briefs 57 (10), 777-781, 2010
202010
Gradient—An adaptive fault-tolerant routing algorithm for 2D mesh network-on-chips
I Pratomo, S Pillement
Proceedings of the 2012 Conference on Design and Architectures for Signal …, 2012
182012
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
B Miramond, E Huck, F Verdier, A Benkhelifa, B Granado, T Lefebvre, ...
International Journal of Reconfigurable Computing 2009, 2009
182009
A compilation framework for a dynamically reconfigurable architecture
R David, D Chillet, S Pillement, O Sentieys
International Conference on Field Programmable Logic and Applications, 1058-1067, 2002
182002
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
SMAH Jafri, SJ Piestrak, O Sentieys, S Pillement
Microprocessors and Microsystems 38 (2), 124-136, 2014
172014
Method and device for programming a FPGA
O Sentieys, S Pillement, C Huriaux, A Courtay
US Patent 9,754,061, 2017
162017
Real-Time Scheduling on Heterogeneous System-on-Chip Architectures Using an Optimized Artificial Neural Network
D Chillet, A Eiche, S Pillement, O Sentieys
Journal of Systems Architecture 57 (4), 340--353, 2011
162011
Task placement for dynamic and partial reconfigurable architecture
A Eiche, D Chillet, S Pillement, O Sentieys
2010 Conference on Design and Architectures for Signal and Image Processing …, 2010
162010
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