Brandon Reagen
Brandon Reagen
Assistant Professor, New York University
Verified email at - Homepage
Cited by
Cited by
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators
B Reagen, P Whatmough, R Adolf, S Rama, H Lee, SK Lee, ...
International Symposium on Computer Architecture (ISCA) 43, 267-278, 2016
Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures
YS Shao, B Reagen, GY Wei, D Brooks
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
MachSuite: Benchmarks for Accelerator Design and Customized Architectures
B Reagen, R Adolf, YS Shao, D Wei, Gu-Yeon, Brooks
IISWC, 2014
Fathom: Reference workloads for modern deep learning methods
R Adolf, S Rama, B Reagen, GY Wei, D Brooks
2016 IEEE International Symposium on Workload Characterization (IISWC), 1-10, 2016
Machine learning at facebook: Understanding inference at the edge
CJ Wu, D Brooks, K Chen, D Chen, S Choudhury, M Dukhan, ...
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
Ares: A framework for quantifying the resilience of deep neural networks
B Reagen, U Gupta, L Pentecost, P Whatmough, SK Lee, N Mulholland, ...
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
The aladdin approach to accelerator design and modeling
YS Shao, B Reagen, GY Wei, D Brooks
IEEE Micro 35 (3), 58-70, 2015
The architectural implications of facebook's DNN-based personalized recommendation
U Gupta, CJ Wu, X Wang, M Naumov, B Reagen, D Brooks, B Cottel, ...
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
Deep learning for computer architects
B Reagen, R Adolf, P Whatmough, GY Wei, D Brooks
Synthesis Lectures on Computer Architecture 12 (4), 1-123, 2017
A case for efficient accelerator design space exploration via Bayesian optimization
B Reagen, JM Hernández-Lobato, R Adolf, M Gelbart, P Whatmough, ...
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
Quantifying acceleration: Power/performance trade-offs of application kernels in hardware
B Reagen, YS Shao, GY Wei, D Brooks
International Symposium on Low Power Electronics and Design (ISLPED), 395-400, 2013
On-chip deep neural network storage with multi-level eNVM
M Donato, B Reagen, L Pentecost, U Gupta, D Brooks, GY Wei
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
Designing neural network hardware accelerators with decoupled objective evaluations
JM Hernández-Lobato, MA Gelbart, B Reagen, R Adolf, ...
NIPS workshop on Bayesian Optimization, 10, 2016
A multi-chip system optimized for insect-scale flapping-wing robots
X Zhang, M Lok, T Tong, S Chaput, SK Lee, B Reagen, H Lee, D Brooks, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), C152-C153, 2015
Weightless: Lossy weight encoding for deep neural network compression
B Reagan, U Gupta, B Adolf, M Mitzenmacher, A Rush, GY Wei, D Brooks
International Conference on Machine Learning, 4324-4333, 2018
A fully integrated battery-powered system-on-chip in 40-nm CMOS for closed-loop control of insect-scale pico-aerial vehicle
X Zhang, M Lok, T Tong, SK Lee, B Reagen, S Chaput, PEJ Duhamel, ...
IEEE Journal of Solid-State Circuits 52 (9), 2374-2387, 2017
Masr: A modular accelerator for sparse rnns
U Gupta, B Reagen, L Pentecost, M Donato, T Tambe, AM Rush, GY Wei, ...
2019 28th International Conference on Parallel Architectures and Compilation …, 2019
Maxnvm: Maximizing dnn storage density and inference efficiency with sparse encoding and error mitigation
L Pentecost, M Donato, B Reagen, U Gupta, S Ma, GY Wei, D Brooks
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
DeepRecSys: A System for Optimizing End-To-End At-scale Neural Recommendation Inference
U Gupta, S Hsia, V Saraph, X Wang, B Reagen, GY Wei, HHS Lee, ...
arXiv preprint arXiv:2001.02772, 2020
Using dynamic dependence analysis to improve the quality of high-level synthesis designs
R Garibotti, B Reagen, YS Shao, GY Wei, D Brooks
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
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