Luis Gabriel Murillo
Luis Gabriel Murillo
CTO, Silexica GmbH
Bestätigte E-Mail-Adresse bei
Zitiert von
Zitiert von
Model-based design space exploration for RTES with SysML and MARTE
M Mura, LG Murillo, M Prevostini
2008 Forum on Specification, Verification and Design Languages, 203-208, 2008
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface
RL Bücs, L Murillo, E Korotcenko, G Dugge, R Leupers, G Ascheid, ...
Languages, design methods, and tools for electronic system design, 3-28, 2016
Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs
MA Aguilar, R Leupers, G Ascheid, LG Murillo
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms
PS Paolucci, A Biagioni, LG Murillo, F Rousseau, L Schor, L Tosoratto, ...
Journal of Systems Architecture 69, 29-53, 2016
Automatic detection of concurrency bugs through event ordering constraints
LG Murillo, S Wawroschek, J Castrillon, R Leupers, G Ascheid
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
Pre-architectural performance estimation for ASIP design based on abstract processor models
JF Eusse, C Williams, LG Murillo, R Leupers, G Ascheid
2014 International Conference on Embedded Computer Systems: Architectures …, 2014
Synchronization for hybrid MPSoC full-system simulation
LG Murillo, J Eusse, J Jovic, S Yakoushkin, R Leupers, G Ascheid
DAC Design Automation Conference 2012, 121-126, 2012
Backend for virtual platforms with hardware scheduler in the MAPS framework
J Castrillon, A Shah, LG Murillo, R Leupers, G Ascheid
2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2011
EURETILE design flow: Dynamic and fault tolerant mapping of multiple applications onto many-tile systems
L Schor, I Bacivarov, LG Murillo, PS Paolucci, F Rousseau, A El Antably, ...
2014 IEEE International Symposium on Parallel and Distributed Processing …, 2014
Semi-automated Hw/Sw Co-design for embedded systems: from MARTE models to SystemC simulators
LG Murillo, M Mura, M Prevostini
2009 Forum on Specification & Design Languages (FDL), 1-6, 2009
Scalable and retargetable debugger architecture for heterogeneous MPSoCs
LG Murillo, J Harnath, R Leupers, G Ascheid
Proceedings of the 2012 System, Software, SoC and Silicon Debug Conference, 1-6, 2012
DVFS-enabled power-performance trade-off in MPSoC SW application mapping
G Onnebrink, F Walbroel, J Klimt, R Leupers, G Ascheid, LG Murillo, ...
2017 International Conference on Embedded Computer Systems: Architectures …, 2017
Parallel SystemC simulation for ESL design
JH Weinstock, LG Murillo, R Leupers, G Ascheid
ACM Transactions on Embedded Computing Systems (TECS) 16 (1), 1-25, 2016
MDE support for HW/SW codesign: A UML-based design flow
LG Murillo, M Mura, M Prevostini
Advances in design methods from modeling languages for embedded systems and …, 2010
Robot Teleoperation System Based on GPRS
ND Muñoz, JF Eusse, EJ Cruz
Electronics, Robotics and Automotive Mechanics Conference (CERMA 2007), 74-79, 2007
SWAT: Assertion-based debugging of concurrency issues at system level
LG Murillo, RL Bücs, D Hincapie, R Leupers, G Ascheid
The 20th Asia and South Pacific Design Automation Conference, 600-605, 2015
Deterministic event-based control of Virtual Platforms for MPSoC software debugging
LG Murillo, RL Buecs, R Leupers, G Ascheid
2015 International Conference on Embedded Computer Systems: Architectures …, 2015
Bridging the Gap Between Model Driven Engineering and HW/SW Codesign
LG Murillo
University of Lugano - ALaRI, Switzerland, 2009
Application-specific architecture exploration based on processor-agnostic performance estimation
JF Eusse, LG Murillo, C McGirr, R Leupers, G Ascheid
Proceedings of the 18th International Workshop on Software and Compilers for …, 2015
Hybrid simulation for extensible processor cores
J Jovic, S Yakoushkin, L Murillo, J Eusse, R Leupers, G Ascheid
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 288-291, 2012
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