| A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning X Wu, V Saxena, K Zhu, S Balagopal IEEE Transactions on Circuits and Systems II: Express Briefs 62 (11), 1088-1092, 2015 | 160 | 2015 |
| Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs RMR Koppula, S Balagopal, V Saxena 2011 IEEE International SOC Conference, 380-385, 2011 | 17 | 2011 |
| A low-power single-bit continuous-time δσ converter with 92.5 db dynamic range for biomedical applications S Balagopal, V Saxena Journal of Low Power Electronics and Applications 2 (3), 197-209, 2012 | 13 | 2012 |
| An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC S Balagopal, SU Ay 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 373-376, 2009 | 12 | 2009 |
| Systematic design of three-stage op-amps using split-length compensation V Saxena, S Balagopal, RJ Baker 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 9 | 2011 |
| Systematic design of multi-bit continuous-time delta-sigma modulators using two-step quantizer S Balagopal, RMR Koppula, V Saxena 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 8 | 2011 |
| Design analysis of a 12.5 GHz PLL in 130 nm SiGe BiCMOS process K Zhu, V Saxena, X Wu, S Balagopal 2015 IEEE Workshop on Microelectronics and Electron Devices (WMED), 1-4, 2015 | 7 | 2015 |
| A 110μW single-bit continuous-time ΔΣ converter with 92.5 dB dynamic range S Balagopal, RM Roy, V Saxena 2010 IEEE Dallas Circuits and Systems Workshop, 1-4, 2010 | 7 | 2010 |
| A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT- ADC with 1.5 cycle quantizer delay and improved STF S Balagopal, K Zhu, V Saxena Analog Integrated Circuits and Signal Processing 78, 275-286, 2014 | 5* | 2014 |
| Systematic design of 10-bit 50MS/s pipelined ADC K Zhu, S Balagopal, V Saxena 2013 IEEE Workshop on Microelectronics and Electron Devices (WMED), 17-20, 2013 | 5 | 2013 |
| Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time\ Delta\ Sigma modulator with 15 MHz bandwidth and 60 dB dynamic range S Balagopal, K Zhu, X Wu, V Saxena Analog Integrated Circuits and Signal Processing, 1-14, 2016 | 4 | 2016 |
| Design of wideband continuous-time ΔΣ ADCs using two-step quantizers S Balagopal, V Saxena 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 4 | 2012 |
| Multi-bit continuous-time delta-sigma modulator for audio application RMR Koppula, S Balagopal, V Saxena 2012 IEEE Workshop on Microelectronics and Electron Devices, 1-5, 2012 | 4 | 2012 |
| Optimizing the control of a hysteretic power converter at low duty cycles JW Lawrence, GG Mackay, S Balagopal US Patent 11,522,460, 2022 | 2 | 2022 |
| High-speed delta-sigma data converters for next-generation wireless communication S Balagopal | 2 | 2014 |
| Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion S Balagopal, K Zhu, V Saxena 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013 | 2 | 2013 |
| Reconfigurable Continuous-Time Delta-Sigma Analog-to-Digital Converters for Software-Defined and Multi-Standard Radios V Saxena, S Balagopal, H Chen | 2 | 2011 |
| Optimizing transitions between operational modes in a bypassable power converter JW Lawrence, GG Mackay, S BALAGOPAL US Patent App. 17/149,338, 2022 | 1 | 2022 |
| Realization of a 10 GHz PLL in IBM 130 nm SiGe BiCMOS process for optical transmitter K Zhu, S Balagopal, X Wu, V Saxena 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 1 | 2017 |
| Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects K Zhu, S Balagopal, V Saxena, W Kuang 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013 | 1 | 2013 |
Vishal SaxenaUniversity of DelawareVerified email at udel.edu
