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Lilia Zaourar
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Maximizing the execution rate of low criticality tasks in mixed criticality system
M Jan, L Zaourar, M Pitel
Proc. WMC, RTSS, 43-48, 2013
752013
Approximation algorithm for scheduling a chain of tasks on heterogeneous systems
M Ait Aba, L Zaourar, A Munier
Euro-Par 2017: Parallel Processing Workshops: Euro-Par 2017 International …, 2018
262018
Co-simulation of a model predictive control system for automotive applications
C Bernardeschi, P Dini, A Domenici, A Mouhagir, M Palmieri, S Saponara, ...
International Conference on Software Engineering and Formal Methods, 204-220, 2021
172021
3DIP: An iterative partitioning tool for monolithic 3D IC
G Berhault, M Brocard, S Thuries, F Galea, L Zaourar
2016 IEEE International 3D Systems Integration Conference (3DIC), 1-5, 2016
122016
Handling criticality mode change in time-triggered systems through linear programming
M Jan, L Zaourar, V Legout, L Pautet
Ada User Journal 35 (2), 133-137, 2014
112014
Efficient algorithm for scheduling parallel applications on hybrid multicore machines with communications delays and energy constraint
M Ait Aba, L Zaourar, A Munier
Concurrency and Computation: Practice and Experience 32 (15), e5573, 2020
102020
Approximation algorithm for scheduling applications on hybrid multi-core machines with communications delays
MA Aba, L Zaourar, A Munier
2018 IEEE International Parallel and Distributed Processing Symposium …, 2018
102018
Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning
F Galea, S Carpov, L Zaourar
2018 IEEE International Parallel and Distributed Processing Symposium …, 2018
92018
A complete methodology for determining memory BIST optimization under wrappers sharing constraints
L Zaourar, Y Kieffer, A Wenzel
2011 3rd Asia Symposium on Quality Electronic Design (ASQED), 46-53, 2011
92011
Multilevel simulation-based co-design of next generation HPC microprocessors
L Zaourar, M Benazouz, A Mouhagir, F Jebali, T Sassolas, JC Weill, ...
2021 International Workshop on Performance Modeling, Benchmarking and …, 2021
82021
Task management on fully heterogeneous micro‐server system: Modeling and resolution strategies
L Zaourar, M Ait Aba, D Briand, JM Philippe
Concurrency and Computation: Practice and Experience 30 (23), e4798, 2018
82018
Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System.
JMP Lilia Zaourar, Massinissa Ait Aba, David Briand
IPDPS HCW Workshops 2017, 65-76, 2017
7*2017
A graph-based approach to optimal scan chain stitching using RTL design descriptions
L Zaourar, Y Kieffer, C Aktouf
VLSI Design 2012, 3-3, 2012
62012
Optimisation du partage de blocs BIST pour filetest des mémoires d’un circuit intégré
L Zaourar, JA Chentoufi, Y Kieffer, A Waserhole
Laboratory G-SCOP, 2010
62010
An innovative methodology for scan chain insertion and analysis at RTL
L Zaourar, Y Kieffer, C Aktouf
2011 Asian Test Symposium, 66-71, 2011
52011
Cross-level co-simulation and verification of an automatic transmission control on embedded processor
C Bernardeschi, A Domenici, M Palmieri, S Saponara, T Sassolas, ...
Software Engineering and Formal Methods. SEFM 2020 Collocated Workshops …, 2021
42021
Decoupling processor and memory hierarchy simulators for efficient design space exploration
F Jebali, O Matoussi, A Wicaksana, A Charif, L Zaourar
System Engineering for constrained embedded systems, 47-52, 2022
22022
Optimisation de contre-mesure à l'insertion de Hardware Trojan
J Fontaine, L Zaourar, R Chotin
22ème Conférence ROADEF de la société Française de Recherche Opérationnelle …, 2021
22021
A multi-objective optimization for memory BIST sharing using a genetic algorithm
L Zaourar, Y Kieffer, A Wenzel
2011 IEEE 17th International On-Line Testing Symposium, 73-78, 2011
22011
A global optimization for scan chain insertion at the RT-level
L Zaourar, Y Kieffer, C Aktouf
IEEE Annual Symposium on VLSI 2011, 321-322, 2011
22011
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Articles 1–20