Frank K. Gürkaynak
Frank K. Gürkaynak
Senior Scientist, ETH Zurich
Verified email at ee.ethz.ch - Homepage
TitleCited byYear
Power-Analysis Attack on an ASIC AES implementation
SB Ors, F Gurkaynak, E Oswald, B Preneel
International Conference on Information Technology: Coding and Computing …, 2004
2562004
Globally asynchronous, locally synchronous circuits: Overview and outlook
M Krstic, E Grass, FK Gürkaynak, P Vivet
IEEE Design & Test of Computers 24 (5), 430-441, 2007
2462007
Red team vs. blue team hardware Trojan analysis: detection of a hardware Trojan on an actual ASIC
M Muehlberghuber, FK Gürkaynak, T Korak, P Dunst, M Hutter
Proceedings of the 2nd International Workshop on Hardware and Architectural …, 2013
992013
Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
752017
Efficient ASIC implementation of a real-time depth mapping stereo vision system
M Kuhn, S Moser, O Isler, FK Gurkaynak, A Burg, N Felber, H Kaeslin, ...
2003 46th Midwest Symposium on Circuits and Systems 3, 1478-1481, 2003
742003
Efficient ASIC implementation of a real-time depth mapping stereo vision system
M Kuhn, S Moser, O Isler, FK Gurkaynak, A Burg, N Felber, H Kaeslin, ...
2003 46th Midwest Symposium on Circuits and Systems 3, 1478-1481, 2003
742003
Self-timed ring for globally-asynchronous locally-synchronous systems
T Villiger, H Kaslin, FK Gurkaynak, S Oetiker, W Fichtner
Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003
662003
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
622017
Breaking ECC2K-130.
DV Bailey, L Batina, DJ Bernstein, P Birkner, JW Bos, HC Chen, ...
IACR Cryptology ePrint Archive 2009, 541, 2009
582009
GALS at ETH Zurich: Success or failure?
FK Gurkaynak, S Oetiker, H Kaeslin, N Felber, W Fichtner
12th IEEE International Symposium on Asynchronous Circuits and Systems …, 2006
542006
Towards an AES crypto-chip resistant to differential power analysis
N Pramstaller, FK Gurkaynak, S Haene, H Kaeslin, N Felber, W Fichtner
Proceedings of the 30th European Solid-State Circuits Conference, 307-310, 2004
542004
A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ...
Solid-State Electronics 117, 170-184, 2016
492016
Developing a hardware evaluation method for SHA-3 candidates
L Henzen, P Gendotti, P Guillet, E Pargaetzi, M Zoller, FK Gürkaynak
International Workshop on Cryptographic Hardware and Embedded Systems, 248-263, 2010
462010
2Gbit/s hardware realizations of RIJNDAEL and SERPENT: A comparative analysis
AK Lutz, J Treichler, FK Gürkaynak, H Kaeslin, G Basler, A Erni, ...
International Workshop on Cryptographic Hardware and Embedded Systems, 144-158, 2002
382002
Improving DPA security by using globally-asynchronous locally-synchronous systems
F Gurkaynak, S Oetiker, H Kaeslin, N Felber, W Fichtner
Proceedings of the 31st European Solid-State Circuits Conference, 2005 …, 2005
352005
A Masked AES ASIC Implementation
N Pramstaller, E Oswald, S Mangard, FK Gürkaynak, S Häne
na, 2004
332004
A functional test methodology for globally-asynchronous locally-synchronous systems
FK Gurkaynak, T Villiger, S Oetiker, N Felber, H Kaeslin, W Fichtner
Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002
312002
193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ...
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016
302016
Interface layering phenomena in capacitance detection of DNA with biochips
S Carrara, FK Gürkaynak, C Guiducci, C Stagni, L Benini, Y Leblebici, ...
Sensors & Transducers Journal 76 (ARTICLE), 969-977, 2007
292007
A generic standard cell design methodology for differential circuit styles
S Badel, E Güleyüpoǧlu, Ö İnaç, AP Martinez, P Vietti, FK Gürkaynak, ...
Proceedings of the conference on Design, automation and test in Europe, 843-848, 2008
282008
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