| Polly-Polyhedral optimization in LLVM T Grosser, H Zheng, R Aloor, A Simbürger, A Größlinger, LN Pouchet Proceedings of the First International Workshop on Polyhedral Compilation …, 2011 | 244 | 2011 |
| Fast and effective placement and routing directed high-level synthesis for FPGAs H Zheng, ST Gurumani, K Rupnow, D Chen Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 37 | 2014 |
| High-level synthesis with behavioral-level multicycle path analysis H Zheng, ST Gurumani, L Yang, D Chen, K Rupnow IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 33 | 2014 |
| 1024-point pipeline FFT processor with pointer FIFOs based on FPGA G Zhong, H Zheng, ZH Jin, D Chen, Z Pang 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 122-125, 2011 | 13 | 2011 |
| A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis H Zheng, Q Liu, J Li, D Chen, Z Wang 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 780-786, 2013 | 7 | 2013 |
| Optimizing memory-access patterns for deep learning accelerators H Zheng, S Oh, H Wang, P Briggs, J Gai, A Jain, Y Liu, R Heaton, ... arXiv preprint arXiv:2002.12798, 2020 | 5 | 2020 |
| A., Größsslinger, A. and Pouchet, L.-N. 2011. Polly-Polyhedral optimization in LLVM T Grosser, H Zheng First International Workshop on Polyhedral Compilation Techniques (IMPACT'11 …, 2011 | 4 | 2011 |
| New solutions for system-level and high-level synthesis W Zuo, H Zheng, ST Guruman, K Rupnow, D Chen 2014 International Symposium on Integrated Circuits (ISIC), 71-74, 2014 | 3 | 2014 |
| Efficient utilization of processing element array JT Huynh, R Diamant, H Zheng, Y Liu, A Jain, Y Wang, V Sharma, ... US Patent App. 16/698,461, 2021 | 2 | 2021 |
| Loop-oriented neural network compilation H Zheng, PP Briggs, TJKE von Koch, T Kim, RR Huang US Patent 11,144,291, 2021 | 1 | 2021 |
| State buffer memloc reshaping Y Yu, H Zheng, Q Liu US Patent 11,494,321, 2022 | | 2022 |
| Compilation time reduction for memory and compute bound neural networks H Zheng, RR Huang, RJ Heaton US Patent 11,461,662, 2022 | | 2022 |
| Hierarchical partitioning of operators A Jain, Y Liu, H Zheng, JT Huynh, H Li, D Borkovic, J Zejda, RJ Heaton, ... US Patent App. 16/698,236, 2021 | | 2021 |
Swathi T. GurumaniEngineering ManagerVerified email at multicorewareinc.com
