| A fully-synthesizable single-cycle interconnection network for shared-L1 processor clusters A Rahimi, I Loi, MR Kakoee, L Benini 2011 Design, Automation & Test in Europe, 1-6, 2011 | 150 | 2011 |
| At-speed distributed functional testing to detect logic and delay faults in NoCs MR Kakoee, V Bertacco, L Benini IEEE Transactions on Computers 63 (3), 703-717, 2013 | 77 | 2013 |
| A distributed and topology-agnostic approach for on-line NoC testing MR Kakoee, V Bertacco, L Benini Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on …, 2011 | 74 | 2011 |
| Modified pseudo LRU replacement algorithm H Ghasemzadeh, S Mazrouee, MR Kakoee 13th Annual IEEE International Symposium and Workshop on Engineering of …, 2006 | 69 | 2006 |
| ReliNoC: A reliable network for priority-based on-chip communication MR Kakoee, V Bertacco, L Benini 2011 Design, Automation & Test in Europe, 1-6, 2011 | 51 | 2011 |
| Reliable network-on-chip based on generalized de Bruijn graph M Hosseinabady, MR Kakoee, J Mathew, DK Pradhan 2007 IEEE International High Level Design Validation and Test Workshop, 3-10, 2007 | 46 | 2007 |
| Fine-grained power and body-bias control for near-threshold deep sub-micron CMOS circuits MR Kakoee, L Benini IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (2 …, 2011 | 28 | 2011 |
| Variation-tolerant architecture for ultra low power shared-l1 processor clusters MR Kakoee, I Loi, L Benini IEEE Transactions on Circuits and Systems II: Express Briefs 59 (12), 927-931, 2012 | 25 | 2012 |
| Low latency and energy efficient scalable architecture for massive NoCs using generalized de Bruijn graph M Hosseinabady, MR Kakoee, J Mathew, DK Pradhan IEEE transactions on very large scale integration (VLSI) systems 19 (8 …, 2010 | 25 | 2010 |
| Architecture support for tightly-coupled multi-core clusters with shared-memory HW accelerators M Dehyadegari, A Marongiu, MR Kakoee, S Mohammadi, N Yazdani, ... IEEE Transactions on Computers 64 (8), 2132-2144, 2014 | 22 | 2014 |
| A tightly-coupled multi-core cluster with shared-memory HW accelerators M Dehyadegari, A Marongiu, MR Kakoee, L Benini, S Mohammadi, ... 2012 international conference on embedded computer systems (SAMOS), 96-103, 2012 | 20 | 2012 |
| Automatic synthesis of near-threshold circuits with fine-grained performance tunability MR Kakoee, A Sathanur, A Pullini, J Huisken, L Benini Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010 | 20 | 2010 |
| Using integer equations for high level formal verification property checking B Alizadeh, MR Kakoee Fourth International Symposium on Quality Electronic Design, 2003 …, 2003 | 20 | 2003 |
| Dynamically adaptive voltage-frequency guardband control circuit L Ho, KA Bowman, N Toosizadeh, SHJ Hu, MR Kakoee, SK Kannan US Patent 10,009,016, 2018 | 17 | 2018 |
| Enhancing the testability of RTL designs using efficiently synthesized assertions MR Kakoee, M Riazati, S Mohammadi 9th International Symposium on Quality Electronic Design (isqed 2008), 230-235, 2008 | 17 | 2008 |
| A new physical routing approach for robust bundled signaling on NoC links MR Kakoee, I Loi, L Benini Proceedings of the 20th symposium on Great lakes symposium on VLSI, 3-8, 2010 | 14 | 2010 |
| A new approach for design and verification of transaction level models MR Kakoee, H Shojaei, H Ghasemzadeh, M Sirjani, Z Navabi 2007 IEEE International Symposium on Circuits and Systems (ISCAS), 3760-3763, 2007 | 14 | 2007 |
| HW/SW architecture for soft-error cancellation in real-time operating system K MR, M Daneshtalab, S Safari IEICE Electronics Express 4 (23), 755-761, 2007 | 13 | 2007 |
| A multi-banked shared-l1 cache architecture for tightly coupled processor clusters MR Kakoee, V Petrovic, L Benini 2012 International Symposium on System on Chip (SoC), 1-5, 2012 | 12 | 2012 |
| A resilient architecture for low latency communication in shared-L1 processor clusters MR Kakoee, I Loi, L Benini 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 887-892, 2012 | 12 | 2012 |
Luca BeniniETH Zürich, Università di BolognaAdresse e-mail validée de unibo.it
