| Federated learning based on dynamic regularization DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama arXiv preprint arXiv:2111.04263, 2021 | 417 | 2021 |
| Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ... Proceedings of Machine Learning and Systems 3, 517-532, 2021 | 172 | 2021 |
| Apparatus and method for partitioning a shared cache of a chip multi-processor M Mattina, A Juan-Hormigo, J Emer, R Matas-Navarro US Patent 7,558,920, 2009 | 50 | 2009 |
| Debiasing model updates for improving personalized federated training DAE Acar, Y Zhao, R Zhu, R Matas, M Mattina, P Whatmough, ... International Conference on Machine Learning, 21-31, 2021 | 37 | 2021 |
| Collapsible linear blocks for super-efficient super resolution K Bhardwaj, M Milosavljevic, L O'Neil, D Gope, R Matas, A Chalfin, ... Proceedings of Machine Learning and Systems 4, 529-547, 2022 | 27 | 2022 |
| Simulating a chip multiprocessor with a symmetric multiprocessor KC Barr, R Matas-Navarro, C Weaver, T Juan, J Emer Boston Area Architecture Workshop, 2005 | 18 | 2005 |
| Performing memory accesses using memory context information R Matas US Patent 8,521,944, 2013 | 16 | 2013 |
| Stateless capture of data linear addresses during precise event based sampling R Gramunt, R Matas, BC Chaffin, NS Moyer, R Padmanabhan, AP Suprun, ... US Patent 9,652,237, 2017 | 9 | 2017 |
| UDC: Unified DNAS for compressible TinyML models I Fedorov, R Matas, H Tann, C Zhou, M Mattina, P Whatmough arXiv preprint arXiv:2201.05842, 2022 | 8 | 2022 |
| Dynamic partitioning of execution resources JF Duluk Jr, L Durant, RM Navarro, A Menezes, J Tuckey, G Hirota, ... US Patent 11,307,903, 2022 | 4 | 2022 |
| Dynamic partitioning of execution resources JF Duluk Jr, L Durant, RM Navarro, A Menezes, J Tuckey, G Hirota, ... US Patent 10,817,338, 2020 | 2 | 2020 |
| Resolving memory accesses crossing cache line boundaries R Matas, CL Chan, AP Suprun, A Kesiraju US Patent 10,318,427, 2019 | 2 | 2019 |
| Scalable event handling in multi-threaded processor cores R Gramunt, R Padmanabhan, R Matas, NS Moyer, BC Chaffin, A Sodani, ... US Patent 9,886,396, 2018 | 2 | 2018 |
| Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit SS Chang, A Thakur, R Sundararaman, R Matas, JS Lawlor, RF Netting US Patent 9,372,816, 2016 | 2 | 2016 |
| Initialization of multi-core processing system SS Chang, A Thakur, RC Sundararaman, R Matas US Patent 9,367,329, 2016 | 2 | 2016 |
| Federated learning based on dynamic regularization V Saligrama, DAE Acar, PN Whatmough, R Matas, M Mattina, Y Zhao | 1 | 2022 |
| Stateless capture of data linear addresses during precise event based sampling R Gramunt, R Matas, BC Chaffin, NS Moyer, R Padmanabhan, AP Suprun, ... US Patent 10,175,986, 2019 | 1 | 2019 |
| Memory fault suppression via re-execution and hardware FSM R Matas, R Gramunt, CL Chan, BC Chaffin, A Kesiraju, JC Hall, J Corbal US Patent 9,715,432, 2017 | 1 | 2017 |
| Method and apparatus to share modified data without write-back in a shared-memory many-core system R Sundararaman, JC Mejia, OM Rosell, J Antonio, R Matas US Patent App. 13/731,584, 2014 | 1 | 2014 |
| System, devices and/or processes for designing neural network processing devices I Fedorov, RM Navarro, C Zhou, H Tann, PN Whatmough, M Mattina US Patent App. 17/394,048, 2023 | | 2023 |
Matthew MattinaVerified email at alumni.princeton.edu
