Jannis Stoppe
Jannis Stoppe
Researcher, DFKI
Verified email at informatik.uni-bremen.de
Title
Cited by
Cited by
Year
Data extraction from SystemC designs using debug symbols and the SystemC API
J Stoppe, R Wille, R Drechsler
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 26-31, 2013
232013
AIBA: an Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration
M Goli, J Stoppe, R Drechsler
2016 IEEE 34th International Conference on Computer Design (ICCD), 360-363, 2016
162016
Automated feature localization for dynamically generated SystemC designs
J Stoppe, R Wille, R Drechsler
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 277-280, 2015
132015
Validating SystemC implementations against their formal specifications
J Stoppe, R Wille, R Drechsler
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 1-8, 2014
132014
Automated nonintrusive analysis of electronic system level designs
M Goli, J Stoppe, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
122018
Automatic protocol compliance checking of SystemC TLM-2.0 simulation behavior using timed automata
M Goli, J Stoppe, R Drechsler
2017 IEEE International Conference on Computer Design (ICCD), 377-384, 2017
122017
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications
M Goli, J Stoppe, R Drechsler
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
122017
Verification-driven design across abstraction levels: A case study
N Przigoda, J Stoppe, J Seiter, R Wille, R Drechsler
2015 Euromicro Conference on Digital System Design, 375-382, 2015
122015
Analyzing SystemC designs: SystemC analysis approaches for varying applications
J Stoppe, R Drechsler
Sensors 15 (5), 10399-10421, 2015
122015
Change impact analysis for hardware designs from natural language to system level
M Ring, J Stoppe, C Luth, R Drechsler
2016 Forum on Specification and Design Languages (FDL), 1-7, 2016
82016
Hardware/Software Co-Visualization on the Electronic System Level using SystemC
R Drechsler, J Stoppe
2016 29th International Conference on VLSI Design and 2016 15th …, 2016
82016
Effects of cell shapes on the routability of digital microfluidic biochips
L Schneider, O Keszocze, J Stoppe, R Drechsler
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
72017
Resilience evaluation for approximating SystemC designs using machine learning techniques
M Goli, J Stoppe, R Drechsler
2018 International Symposium on Rapid System Prototyping (RSP), 97-103, 2018
52018
Bioviz: An interactive visualization engine for the design of digital microfluidic biochips
J Stoppe, O Keszocze, M Luenert, R Wille, R Drechsler
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 170-175, 2017
52017
Cone of influence analysis at the electronic system level using machine learning
J Stoppe, R Wille, R Drechsler
2013 Euromicro Conference on Digital System Design, 582-587, 2013
52013
Dealing with highly unbalanced sidescan sonar image datasets for deep learning classification tasks
Y Steiniger, J Stoppe, T Meisen, D Kraus
Global Oceans 2020: Singapore–US Gulf Coast, 1-7, 2020
32020
Revvis: Visualization of structures and properties in reversible circuits
R Wille, J Stoppe, E Schönborn, K Datta, R Drechsler
International Conference on Reversible Computation, 111-124, 2014
32014
Towards a multi-dimensional and dynamic visualization for ESL designs
J Stoppe, M Michael, M Soeken, R Wille, R Drechsler
Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2014
32014
Semi-formal cycle-accurate temporal execution traces reconstruction
R Massoud, J Stoppe, D Große, R Drechsler
International Conference on Formal Modeling and Analysis of Timed Systems …, 2017
22017
Computer: Wie funktionieren Smartphone, Tablet & Co.?
R Drechsler, A Fink, J Stoppe
Springer-Verlag, 2017
12017
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Articles 1–20